CPU Power Management and Debug Microarchitecture & Logic Design Engineer

Rivos is seeking CPU power management experts to join their team in building RISC-V CPUs with class-leading performance, power, security, and RAS features. Responsibilities include developing microarchitecture specifications for power management and debug features, owning RTL development for these features, and collaborating with verification, physical implementation, DFT, and firmware teams. The role also involves working with external IP vendors for integration and evaluating new features using domain knowledge. A Bachelor's, Master's, or PhD in EE or ECE is required.