CPU Power Management and Debug Microarchitecture & Logic Design Engineer

rivos

2+ Years | Santa Clara, California, United States (Hybrid) | Full Time | 13 months ago
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Job Summary

Rivos is seeking CPU power management experts to join their team in building RISC-V CPUs with class-leading performance, power, security, and RAS features. Responsibilities include developing microarchitecture specifications for power management and debug features, owning RTL development for these features, and collaborating with verification, physical implementation, DFT, and firmware teams. The role also involves working with external IP vendors for integration and evaluating new features using domain knowledge. A Bachelor's, Master's, or PhD in EE or ECE is required.

Must Have

  • Develop microarchitecture specs for power management/debug
  • Own RTL development for power management/debug
  • Work with verification, physical implementation, DFT, firmware
  • Evaluate and integrate external IP
  • Propose and evaluate new features
  • Knowledge of modern OoO CPU microarchitectures
  • 2+ years of CPU power management experience
  • Knowledge of synchronous/asynchronous reset flows
  • Knowledge of active/idle power management techniques
  • Proficient in SystemVerilog

Good to Have

  • Knowledge of coherent memory/bus protocols (AMBA, APB, SPI, I2C)
  • Knowledge of RISC-V ISA

Job Description

Rivos is on a mission to build the best RISC-V enterprise systems in the world with class leading performance, power, security and RAS features. We are seeking CPU power management experts to join our team in building the best RISC-V CPUs in the world.

Responsibilities

    • Develop microarchitecture specifications for power management and debug features
    • Own RTL development of power management and debug features 
    • Work with verification, physical implementation, DFT and firmware teams to deliver a design which meets functional, performance, power and requirements
    • Work with external IP vendors to evaluate and integrate IP into the design
    • Use domain knowledge to propose and evaluate new features

Requirements

    • Knowledge of modern OoO CPU microarchitectures
    • 2+ years of relevant industry experience in CPU power management
    • Knowledge of synchronous and asynchronous reset flows
    • Knowledge or experience with active and idle power management techniques
    • Proficient in SystemVerilog
    • Knowledge of coherent memory and bus protocols (AMBA, APB, SPI, I2C, etc.) is a plus but not required
    • Knowledge of RISC-V ISA is a plus but not required
Education
Bachelor’s, Master’s or PhD in EE or ECE