Design-for-Test (DFT) Engineer - Singapore

The Design-for-Test (DFT) Engineer will be a core member of the Silicon Platform Team, focusing on chip development. This role involves comprehensive DFT-related work for SoC chips, including Scan, MBIST, ATPG, Boundary Scan, and IP testing. The engineer will collaborate with STA, physical design, and power engineers to debug timing/power-IR issues and partner with test engineers for silicon test vector bring-up. Candidates should have a Master's degree and over 2 years of DFT experience, with proficiency in scripting and DFT EDA tools.

Must Have

• Responsible for DFT-related work in SoC chips, including Scan, MBIST, ATPG, Boundary Scan, IP test.
• Collaborate with STA, physical design, and power engineers to debug and resolve DFT-related Timing/Power-IR problems.
• Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing.
• Master's degree or above, majoring in Microelectronics, Electronics, Computer Science or related fields.
• More than 2 years of DFT work experience.
• Proficient in scripting skills (such as TCL, Perl, Python).
• Skilled in using DFT EDA tools and mastering DFT principles and methods.

Good to Have

• Familiarity with synthesis/STA.
• Good team spirit and a serious and responsible work attitude.
• Good communication skills and fluent in English reading and writing.

Team Introduction

The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and Electromagnetic Compatibility (Power/IR/EM). The team also oversees tape-out, mass production, packaging, testing, and board-level verification. They collaborate closely with front-end chip teams across business units to drive R&D progress and mass production deployment for chip.

Responsibilities

1. Responsible for DFT-related work in SoC chips, including Scan, MBIST, ATPG, Boundary Scan, IP test etc.

2. Collaborate closely with STA, physical design, and power engineers to debug and resolve DFT-related Timing/Power-IR problems.

3. Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing.

Qualifications

Minimum Qualifications

1. Master's degree or above, majoring in Microelectronics, Electronics, Computer Science or related fields, with more than 2 years of DFT work experience.

2. Proficient in scripting skills (such as TCL, Perl, Python, etc.).

3. Skilled in using DFT EDA tools and mastering DFT principles and methods.

Preferred Qualifications

1. Familiarity with synthesis/STA is preferred.

2. Good team spirit and a serious and responsible work attitude.

3. Good communication skills and fluent in English reading and writing.