Design Verification Engineer

2 Months ago • All levels • Software Development & Engineering • $166,600 PA - $296,300 PA

Job Summary

Job Description

As a Design Verification Engineer, your primary responsibility is to ensure the first silicon of a part of the SoC/IP is free of bugs. You will develop detailed test and coverage plans based on the micro-architecture, suitable verification methodologies, and scalable and portable environments. This includes developing verification environments with stimulus, checkers, assertions, trackers, and coverage. You will create and execute verification plans, bring up designs, enable regression features, and debug test failures. You will also contribute to block, IP, and SoC level test-benches and track and report DV progress.

Job Details

In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Furthermore, you will develop verification plans for all features under your care, execute verification plans, including design bring-up, DV environment bring- up, regression enabling features, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage.

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