Design Verification Engineer

As a Design Verification Engineer, your primary responsibility is to ensure the first silicon of a part of the SoC/IP is free of bugs. You will develop detailed test and coverage plans based on the micro-architecture, suitable verification methodologies, and scalable and portable environments. This includes developing verification environments with stimulus, checkers, assertions, trackers, and coverage. You will create and execute verification plans, bring up designs, enable regression features, and debug test failures. You will also contribute to block, IP, and SoC level test-benches and track and report DV progress.