DFT Engineer- 7+ years

1 Year ago • 7 Years +

Job Summary

Job Description

DFT Engineer with 7+ years experience in Scan Insertion, ATPG, BIST techniques, and on-chip compression techniques. Experience in DFT tools, ATPG, and scan compression.

Must have:

DFT Basics
Scan Insertion
ATPG Tools
BIST Techniques

Good to have:

MBIST Knowledge
Synthesis Knowledge
Post-silicon Debug
Tessent Scan

Perks:

AMD Culture
Transforming Lives

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Job Details

Overview:

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_

Responsibilities:

MTS SILICON DESIGN ENGINEER - DFT

THE ROLE:

As a member of the RTG SoC DFT Team, the successful candidate will own the DFT responsibilities for the next gen of AMD SoCs.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

The candidate must have thorough knowledge of DFT basics such as scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Need to work with product engineering team for Silicon Bring-up and also support post-silicon debug.

Interfacing with the design teams to ensure DFT design rules and guidelines are met
Interact with PD and Front End Integration team for Scan Insertion
Generating high quality manufacturing test patterns for stuck-at, transition fault models and CA model
Simulating and verifying the ATPG and LBIST patterns
Working with the product engineering teams on the delivery of manufacturing test patterns
Developing, enhancing and maintaining scripts as necessary
Able to technically guide and mentor junior folks in the team

PREFERRED EXPERIENCE:

Experience in creating and implementing complex chip-level DFT architecture
Experience in DFT implementation including Scan insertion, ATPG and Simulations
Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression
Experience in debugging low coverage and DRC fixes
Proficient in logic design using Verilog
Experience of debugging test pattern issues
Support the Silicon bringup activities to guarantee highest stability of the test pattern
Knowledge of MBIST is a plus.
Knowledge of synthesis is a plus
Experience with post-silicon debug
Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc
Any Tessent Scan/ATPG certifications is a plus
Excellent presentation and inter-communication skills.

ACADEMIC CREDENTIALS:

Bachelors or Masters degree in computer engineering/Electrical Engineering
Prior experience as DFT engineer

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Qualifications:

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.