GPU Physical Design Engineer

As a GPU Physical Design Engineer in Apple's Silicon Technologies group, you will contribute to the design and manufacturing of next-generation, high-performance, power-efficient GPUs. This role involves strategic engineering and hands-on experience in physical design and large chip integration, implementing complete chip designs from RTL to tapeout. You will work closely with the Front-End team, optimize for performance, power, and area (PPA) in the latest technology nodes, and drive methodologies to streamline physical design work.

Must Have

• Work closely with the FE team to understand chip architecture and drive physical aspects early in design cycle.
• Drive outstanding PD construction and optimization recipes for performance, power and Area (PPA).
• Work on pioneering designs in the latest technology nodes.
• Collaborate to drive methodologies and “best known methods” to streamline PD work.
• Drive the work among place and route engineers, set goals and breakthroughs, plan short and long-term work.
• Lead and resolve design and flow issues related to physical design.
• Bachelors degree in Engineering or Computer Science.
• Experience or coursework in physical design, synthesis, DFT or clocking.
• Experience or coursework with digital logic design, RTL, CMOS transistor logics or VLSI concepts.
• Experience with scripting languages such as TCL, Python, Perl or shell scripting.

Good to Have

• Masters degree.
• Ability in all aspects of ASIC implementation including Synthesis, DFT insertion, Floorplanning, Clock and Power distribution, Place and Route and all aspects of timing, electrical and physical signoff.
• Experience working with EDA tools and exposure to their APIs.
• Use design knowledge and innovative physical construction and optimization flows to push performance, power, and Area (PPA) of GPU designs.
• Knowledge of multi-voltage, power gated, and power retention concepts will be an advantage.
• Practical knowledge with hierarchical design approach, top-down design, budgeting, timing, and physical convergence will be an asset.

Do you love creating sophisticated solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient GPU! You’ll ensure products and services can seamlessly handle the tasks that make them beloved by millions! Joining this group means crafting and building the technology that fuels devices. Together, we enable our customers to do all the things they love with their devices. This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to tapeout.

• Work closely with the FE team to understand chip architecture and drive physical aspects early in design cycle.
• Drive outstanding PD construction and optimization recipes for performance, power and Area (PPA).
• Work on pioneering designs in the latest technology nodes.
• Collaborate to drive methodologies and “best known methods” to streamline PD work, come up with guidelines and checklists, drive execution, and supervise progress.
• Drive the work among place and route engineers, set goals and breakthroughs, plan short and long-term work, understand dependencies between different domains like top, STA, block PnR.
• Lead and resolve design and flow issues related to physical design, identify potential solutions and drive execution.

• Bachelors degree in Engineering or Computer Science required.
• Experience or coursework in one or more of the following areas: physical design, synthesis, DFT or clocking.
• Experience or coursework with digital logic design, RTL, CMOS transistor logics or VLSI concepts.
• Experience with scripting languages such as TCL, Python, Perl or shell scripting.

• Masters degree preferred.
• We value ability in all aspects of ASIC implementation including Synthesis, DFT insertion, Floorplanning, Clock and Power distribution, Place and Route and all aspects of timing, electrical and physical signoff.
• Experience working with EDA tools and exposure to their APIs.
• Use design knowledge and innovative physical construction and optimization flows to push performance, power, and Area (PPA) of GPU designs.
• Knowledge of multi-voltage, power gated, and power retention concepts will be an advantage.
• Practical knowledge with hierarchical design approach, top-down design, budgeting, timing, and physical convergence will be an asset.