IC Verification Engineer

The IC Verification Engineer will be responsible for building test plans, writing functional coverage, and developing scalable and reusable testbenches using verification methodologies. Key duties include creating pseudo-random tests, debugging regression failures, analyzing coverage gaps, and improving tests to ensure thorough verification of the DUT. The role requires innovative thinking to stress the DUT efficiently and documenting the verification strategy.

Must Have

• Build Test plans with all features for Block/Core/SoC and Write Functional Coverage for the features, participate in Reviews
• Write scalable and re-usable testbenches, using the framework of the verification methodology
• Develop Psuedo-random tests to verify and get to full Functional Coverage
• Debug Regression failures, analyze Functional coverage gaps and improve tests to cover the gaps
• Think differently and out-of-the-box to stress the DUT and verify it in an efficient way
• Document verification strategy including Test plans, Testbench, Random tests, etc.
• Bachelor's degree in Electrical Engineering or related degree and 5+ years related experience or Master's degree in Electrical Engineering or related degree and 3+ years related experience
• Must have working knowledge of System Verilog and Verification methodologies like UVM/VMM
• Should have good command over fundamental OOP principles
• Have experience writing Functional Coverage, pseudo random tests

Good to Have

• Knowledge of PCI Express protocol

Job Description:

Job duties include:

• Build Test plans with all features for Block/Core/SoC and Write Functional Coverage for the features, participate in Reviews
• Write scalable and re-usable testbenches, using the framework of the verification methodology
• Develop Psuedo-random tests to verify and get to full Functional Coverage
• Debug Regression failures, analyze Functional coverage gaps and improve tests to cover the gaps
• Think differently and out-of-the-box to stress the DUT and verify it in an efficient way.
• Document verification strategy including Test plans, Testbench, Random tests, etc.

Requirements:

• Bachelor's degree in Electrical Engineering or related degree and 5+ years related experience or Master's degree in Electrical Engineering or related degree and 3+ years related experience
• Must have working knowledge of System Verilog and Verification methodologies like UVM/VMM
• Should have good command over fundamental OOP principles.
• Have experience writing Functional Coverage, pseudo random tests
• Knowledge of PCI Express protocol is a plus