IC Verification Engineer

Architect and develop scalable and reusable Testbench environments using Verification Methodologies. Drive test plans, functional coverage, and build pseudo-random tests for Block/Core/SOC verification. Debug regression failures, analyze coverage gaps, and improve tests. Lead documentation of verification strategy and drive quality improvements, guiding junior team members.

Must Have

• Architect and develop scalable and reusable Testbench environment using Verification Methodologies.
• Drive Test plans for Block/Core/SOC features and write Functional coverage.
• Build pseudo-random tests for full Functional coverage and verification closure.
• Debug Regression failures, analyze Functional Coverage gaps, and improve tests.
• Guide/mentor junior team members.
• Lead documentation of verification strategy and reviews with design/architecture.
• Drive Verification quality and Efficiency improvements.
• Bachelor's with 12+ years or Master's with 10+ years experience in Electrical/Electronics/Equivalent.
• Decade+ experience in complex Verification Environments, Test plans, Functional coverage, pseudo-random testing.
• Full ASIC cycle experience from Architecture development to Tapeout with verification focus.
• Proficient in System Verilog and Verification Methodologies like UVM/VMM.
• Good debug skills for regression failures and understanding complex designs.
• Understanding of complex protocols like PCI Express or other multi-layered protocols.

Good to Have

• Experience in PCIe protocol.
• Scripting knowledge of Python or Perl.
• Comfort with Makefiles.
• Experience with Verifying with other protocols like AXI.

Job duties include:

• Architect and develop scalable and reusable Testbench environment using the framework of Verification Methodologies.
• Drive Test plans for all features for Block/Core/SOC and Write Functional coverage for these features.
• Build pseudo-random tests to verify and get to full Functional coverage and bring the Verification to closure
• Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps
• Work with other members of the team, guide/mentor junior team members
• Think differently and out-of-the-box to stress the DUT and verify it in an efficient way.
• Lead the documentation of verification strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture.
• Driver Verification quality and Efficiency improvements

Mandatory Requirements:

• Bachelor's degree in Electrical/Electronics/Equivalent with 12+ years of experience of Masters degree in Electrical/Electronics/Equivalent with 10+ years of experience
• Decade+ experience in developing complex Verification Environments, developing Test plans, Functional coverage and pseudo-random testing
• Must have gone through a full ASIC cycle right from Architecture development to Tapeout with full focus on Verification
• Very proficient in System Verilog and Verification Methodologies like UVM/VMM
• Good debug skills in analyzing regression failures and understanding of complex designs
• A good understanding of a complex protocol like PCI Express or other multi-layered protocol
• Work with the team and mentor junior engineers

These requirements are a plus:

• Experience in PCIe protocol
• Scripting knowledge of Python or Perl
• Comfort with Makefiles
• Experience with Verifying with other protocols like AXI