Lead - Physical Verification

Implementation with emphasis on Physical Verification & project finishing/tapeout activities

Own and execute Physical Verification flow with in-depth experience in analysing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues ( Calibre/ICV )

Own and execute PV activities at the block and sub-system levels

Work closely with PD team in addressing PV issues and provide solutions

Contribute to SoC-level PV sign-off checks

10+ years of Physical verification experience

Experience with physical verification checks - DRC, LVS, Antenna, ERC, PERC, ESD etc. using Calibre/ICV

Excellent debugging skills and experience with fixing base DRC, metal DRC, especially w.r.t. double/triple patterning layers in advanced process nodes

Hands-on experience in DRC/LVS fixing in Innovus/Fusion Compiler environment is a must

Good hands-on LVS/antenna debug/fixes along with exposure to runtime reduction techniques

Good understanding and hands-on scripting skills in Unix, Perl, Python, SVRF and Tcl to enable high-quality and on-time tapeouts

Good understanding of full chip integration and flows is a plus

Competitive Compensation Package

Restricted Stock Units (RSUs)

Provisions to pursue advanced education from Premium Institute, eLearning content providers

Medical Insurance and a cohort of Wellness Benefits

Educational Assistance

Advance Loan Assistance

Office lunch & Snacks Facility