Memory Controller Verification Engineer

Rivos is seeking Memory Controller design verification engineers to build world-class enterprise SOCs with leading performance, power, security, and RAS features. The role involves verifying DDR and HBM memory subsystem designs, including functional, performance, DFD, and DFT aspects. Responsibilities include collaborating with architects and designers, validating third-party IP integrations, developing test plans and testbenches using SystemVerilog/UVM, integrating VIPs, debugging, managing regressions, ensuring coverage closure, and supporting emulation and silicon bring-up teams. The engineer will also provide debug support across global teams.