Rivos is seeking Memory Controller design verification engineers to join their team and build high-performance memory interfaces for enterprise SOCs. The role involves verifying DDR and HBM memory subsystem designs, including functional, performance, DFD, and DFT features. Responsibilities include collaborating with architects and design teams, validating third-party IP integration, developing test plans and testbenches using SystemVerilog/UVM, integrating VIPs, creating test stimulus and checkers, debugging, regression, coverage closure, and supporting emulation and silicon bring-up teams.