Physical Design and Timing Signoff Methodology, Silicon
Job Summary
This role involves driving physical design and sign-off timing methodologies for mobile System on a Chips (SoCs) to enhance power, performance, and area (PPA) and yield. Responsibilities include analyzing power-performance-area trade-offs across methodologies and technologies, collaborating with cross-functional teams (architecture, IPs, design, foundry, CAD, and sign-off methodology), and ensuring optimal timing signoff conditions. The ideal candidate will have experience in timing analysis, physical design, scripting languages (Perl, Tcl, Python), physical design tool automation, and data analysis. A deep understanding of parasitic extraction tools and flows is also essential. The work contributes to developing custom silicon solutions for Google's direct-to-consumer products.
Must Have
- Bachelor's degree in relevant field
- 2+ years experience in timing analysis and physical design
- Scripting experience (Perl, Tcl, Python)
- Drive physical design and timing methodologies
- Analyze power performance area trade-offs
Good to Have
- Experience in physical design tool automation
- Experience in extraction of design parameters
- Knowledge of timing signoff conditions
- Understanding of parasitic extraction tools
Job Description
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 2 years of experience in timing analysis and physical design.
- Experience in one or more scripting languages, such as Perl, Tcl, Python.
Preferred qualifications:
- Experience in physical design tool automation: synthesis, PandR tools.
- Experience in extraction of design parameters, QoR metrics and analyzing data trends.
- Experience in engineering across physical design and level implementation.
- Knowledge of timing signoff conditions and parameters.
- Understanding of parasitic extraction tools and flow.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Drive the physical design and sign-off timing methodologies for mobile System on a Chips (SoC) to push PPA and yield.
- Analyze power performance area trade-offs across different methodologies and technologies.
- Work with cross-functional architecture, IPs, design, foundry, CAD and sign-off methodology teams.