Physical Design Engineer

1 Minute ago • 6 Years + • Software Development & Engineering • $120,000 PA - $192,000 PA

Job Summary

Job Description

Broadcom is looking for a senior level ASIC physical design engineer. In this highly visible role, you will be contributing to SerDes connectivity ASICs for highly integrated data center products.
Must have:
  • Deep knowledge about industry standards in Physical Design, Physical aware synthesis, Floorplanning, CTS and place and route.
  • Experience in developing and implementing Power-grid and high speed clock constraints and specification.
  • Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and block level.
  • Experience with CDC, static timing analysis methodologies and relevant tools.
  • Exposure to SDF annotated simulations with good understanding of parasitic delays.
  • Understanding and experience of mixed signal environments is a must.
  • Familiarity with Virtuoso, Caliber & Redhawk (power analysis) tools.
  • Good understanding of design tape-out to foundries and solid understanding of supply chain for IC Product development.
  • Scripting experience with Perl, Python, tcl, shell and drive to automate flows.
Good to have:
  • Understanding of backend Cadence tools.
  • Deep understanding of Signal Integrity and Power Integrity for High Speed designs.
  • Proactive, collaborative and creative approach to innovation, technical development and consensus facilitation to influence optimal project results.
  • Excellent time and task management, and interpersonal skills.
Perks:
  • Medical plans
  • Dental plans
  • Vision plans
  • 401(K) participation including company matching
  • Employee Stock Purchase Program (ESPP)
  • Employee Assistance Program (EAP)
  • Company paid holidays
  • Paid sick leave
  • Vacation time
  • Paid Family Leave and other leaves of absence

Job Details

Job Description:

Broadcom is looking for a senior level ASIC physical design engineer. In this highly visible role, you will be contributing to SerDes connectivity ASICs for highly integrated data center products.

Qualifications include:

  • MS in Electrical Engineering or Computer Engineering with 6+ years of experience in Physical design.
  • Deep knowledge about industry standards in Physical Design, Physical aware synthesis, Floorplanning, CTS and place and route.
  • Experience in developing and implementing Power-grid and high speed clock constraints and specification.
  • Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and block level.
  • Experience with CDC, static timing analysis methodologies and relevant tools.
  • Exposure to SDF annotated simulations with good understanding of parasitic delays.
  • Understanding and experience of mixed signal environments is a must.
  • Candidates must be familiar with Virtuoso, Caliber & Redhawk (power analysis) tools.
  • Good understanding of design tape-out to foundries and solid understanding of supply chain for IC Product development.
  • Scripting experience with Perl, Python, tcl, shell and drive to automate flows

Highly Desired Qualifications:

  • Understanding of backend Cadence tools.
  • Deep understanding of Signal Integrity and Power Integrity for High Speed designs.
  • Proactive, collaborative and creative approach to innovation, technical development and consensus facilitation to influence optimal project results.
  • Excellent time and task management, and interpersonal skills.

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About The Company

A global infrastructure technology leader built on more than 60 years of innovation, collaboration and engineering excellence.

 

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