Physical Design Intern
Marvell
Job Summary
As a Physical Design Intern at Marvell, you will work with the CAD team to develop next-generation automated design flows and tools. Your responsibilities will include implementing tool flows, defining CAD methodologies, generating scripts, and evaluating tools. You will be involved in place and route, timing closure, backend activities, static timing analysis, and design for testing. Additionally, you will learn and apply design rules, optimize design implementations, write documentation, and present your work to the team. This internship offers training in all necessary skills.
Must Have
- Pursuing a degree in Electronic Engineering or related field.
- Less than 4 final exams remaining or less than six months left to finish the career.
- Thorough and detail-oriented approach.
- Fluency in English, both speaking and writing.
Good to Have
- Experience in circuit design using CAD tools (Synopsys, Cadence, Mentor).
- Good Spanish communication skills (verbal and written).
Perks & Benefits
- Competitive compensation and great benefits.
- Environment of shared collaboration, transparency, and inclusivity.
- Tools and resources to succeed in doing work that matters.
Job Description
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As a key CAD member of Marvell Central Engineering, you will lead in developing next-generation automated design flow and add-on tools. You will be able to use your extensive design and CAD knowledge to define the organization's design methodology and workflow.What You Can Expect
The engineer will implement tool flows, develop and define CAD methodologies, and generate scripts. He or she will evaluate tools and be responsible for place and route, timing closure, and backend activities. The engineer will code in scripting languages such as TCL and Unix shell languages (coding in languages such as Python is also possible). The engineer will be required to perform the following ASIC design tasks:
- Block-level layout implementation and timing closure.
- Static Timing and Crosstalk analysis and timing closure.
- Design For Testing analysis and timing closure.
- Synthesis and Physical synthesis.
- Learn design rules of advanced technology nodes.
- Optimize design implementation in terms of timing, area, and power.
- Write thorough documentation.
- Present and defend your decisions and results to the team.
Appropriate training for all required skills will be provided.
What We're Looking For
- The candidate must be pursuing a degree in Electronic Engineering or a related technical field(s).
- Have less than 4 final exams remaining (+ degree thesis ongoing) or less than six months left to finish the career.
- Must be very thorough and detail-oriented.
- Experience in circuit design using CAD tools (Synopsys, Cadence, Mentor) is valuable.
- Fluency in English, both speaking and writing.
- Good Spanish communication skills (verbal and written).
Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
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