Senior Design Verification Engineer
Job Description
- Experience in SerDes PHY, DSP, and Analog mixed signal.
- Knowledge of UVM and verification techniques.
- Formal Verification and Power-aware UPF verification techniques.
- 4+ years of Design Verification experience.
- Experience with constrained-random verification in System Verilog and UVM.
- Knowledge in Ethernet and PCIe standards.
- Competitive Compensation Package.
- Restricted Stock Units (RSUs).
- Provisions for advanced education.
- Medical Insurance and Wellness Benefits.
- Educational Assistance.
- Advance Loan Assistance.
- Office lunch & Snacks Facility.
The Opportunity
We're looking for the Wavemakers of tomorrow.
Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.
About the job
The Opportunity
We're looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow's future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.
What You'll Do
- Own end-to-end verification of Ethernet, PCIe and UCIe IP subystems
- Build testbenches and analyze test failures to uncover bugs in IP
- Integrate 3rd party VIPs for compliance testing of standard protocols
- You will Build releases of our design IP for customers
- Take on opportunities to lead, plan, and coordinate tasks with team members
- Collaborate closely with IP design, FE design, PD , PV,EM/IR and post-si teams
- Contribute towards the continuous improvement of IP verification methodologies and processes
What You'll Need
- Minimum 4 years of experience into Design Verification
- Experience in SerDes PHY, DSP, and Analog mixed signal is desirable
- Knowledge in Ethernet and PCIe standards is desirable
- An applied understanding of UVM and verification techniques
- Experience with constrained-random verification in System Verilog and UVM
- Formal Verification, and Power-aware UPF verification techniques
- Tools/Languages - System Verilog, UVM, Python, Perl, C/C++
"We have a flexible work environment to support and help employees thrive in personal and professional capacities"
As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:
- Competitive Compensation Package
- Restricted Stock Units (RSUs)
- Provisions to pursue advanced education from Premium Institute, eLearning content providers
- Medical Insurance and a cohort of Wellness Benefits
- Educational Assistance
- Advance Loan Assistance
- Office lunch & Snacks Facility
Equal Employment Opportunity Statement
Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.
