Front-End Design Engineer | RTL & Timing (Staff)

The Opportunity

We're looking for the Wavemakers of tomorrow.

Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.

Our team develops industry-leading high-speed interconnect IP for High Performance Computing and Artificial Intelligence. We are looking for an RTL engineer who loves thinking beyond the block—owning designs from RTL through synthesis, CTS, and final place & route. You will bring a strong RTL mindset to classic back-end challenges, drive power/timing quality, and help develop AI/agent tooling for automation and quality tracking.

What you will do:

• Own front-to-back implementation of complex IP: from micro-architecture & RTL in SystemVerilog to clean handoff for synthesis, CTS, and P&R.
• Synthesis & QoR: run and interpret DC/Fusion reports; guide retiming, pipeline/boundary placement, logic restructuring, constraint cleanup, and RTL optimizations for PPA.
• Timing constraints & reviews: author/maintain SDC (clocks, generated clocks, groups, false/multicycle/min/max paths); perform timing reviews, triage violations, and partner with STA/PD to close MCMM corners.
• Clocking & CTS inputs: help define clock architecture, CTS targets (latency/skew/jitter), exceptions, and boundary timing to achieve robust closure.
• Power analysis & optimization: set up stimulus, generate SAIF/VCD, correlate vector-based power (PTPX), drive clock/power-gating and micro-architectural improvements.
• AI/Agents in the flow: integrate LLM/agents to auto-triage logs & violations, lint constraints, detect regressions, surface QoR deltas, and recommend fixes/ECO candidates; build dashboards for quality tracking.
• Design quality & sign-off hygiene: collaborate on lint/CDC/RDC, FM/LEC; support DFT/test-mode constraints; contribute to UPF/low-power timing considerations.
• Collaboration & mentorship: work tightly with RTL, PD, STA, DV, and DFT; clear documentation including best practices, and mentor peers on front-to-back thinking; strong cross-functional collaboration.

What You'll Need

• Bachelor/Master in Computer/Electrical Engineering (or equivalent) and substantial experience delivering silicon from RTL through PnR.
• SystemVerilog RTL expertise: clean, synthesizable code; strong micro-architecture instincts for PPA; simulation debug; signoff with Formal/LEC (Formality/Conformal), lint/CDC/RDC (SpyGlass).
• Synthesis & STA proficiency: hands-on with Design Compiler / Fusion / PrimeTime; comfortable reading/analyzing QoR and timing reports.
• SDC mastery: clocks, generated clocks, clock groups, exceptions; hierarchical constraints for MCMM sign-off.
• CTS/P&R awareness: practical understanding of ICC2 flows, useful skew, buffering/sizing, and boundary timing effects.
• Power skills: SAIF/VCD workflows, PrimeTime PX, vector- vs vectorless-based power, and power-driven RTL/synthesis techniques.
• Automation mindset: strong Tcl & Python for constraint generation/validation, report mining, dashboards, and CI.
• AI curiosity & delivery: experience or clear enthusiasm for applying LLMs/agents (e.g., log intelligence, constraint linting, violation clustering, ECO suggestions, regression health checks).

Nice to have:

• Familiarity with UPF/low-power implementation; IR/EM-aware considerations; LVF/variation.
• High-speed/mixed-signal interfaces (DDR, PCIe, SerDes) and digital/analog boundary timing.

"We have a flexible work environment to support and help employees thrive in personal and professional capacities"

Salary and Benefits

Your contribution will be recognized with a base salary influenced by your qualifications, experience, location, and the internal equity of our team to ensure fairness and consistency across roles. In addition to our comprehensive benefits package, employees are also eligible for additional compensation opportunities, including Restricted Stock Units (RSUs), short-term incentive program, Retirement & Saving Programs and participation in the Employee Stock Purchase Plan (ESPP)

You'll also be eligible for benefits described as per below:

• Health & Wellness programs that emphasize knowledge and prevention, helping you stay proactive and prepared to manage your health at every stage.
• Comprehensive health plans
• Wellness Spending Account (WSA)
• Employee Assistance Program (EAP)

Time Off

We value the importance of rest and recharge, which is why we offer flexible time off options to support your well-being.

• Paid Vacation
• Paid Holidays
• Parental Leave

Equal Employment Opportunity Statement

Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.