Senior Design Verification Engineer, Silicon
5 Months ago • 8 Years +
Research Development
Job Description
This Senior Design Verification Engineer role at Google involves planning and executing the verification of digital design blocks at the subsystem level. Responsibilities include creating and enhancing verification environments using SystemVerilog and UVM, debugging tests with design engineers, and collaborating with cross-functional teams (architecture, design, Sival, and software) to define SoC verification strategies. The ideal candidate will have 8+ years of experience with verification methodologies and languages like UVM and SystemVerilog, experience developing testbenches and test cases, and strong debugging skills. The role requires proficiency in constrained-random verification and potentially formal verification methods. The engineer will be the primary contact for functional verification of IPs across teams and will contribute to delivering high-quality, performant hardware solutions for Google's products.
Good To Have:
- Master's degree in EE or CS
- Experience with low power, GLS, formal verification
- Experience leading design verification of IPs
- Experience with subsystem-level verification
Must Have:
- 8+ years experience in verification methodologies (UVM, SystemVerilog)
- Experience developing and maintaining verification testbenches
- Proficiency in constrained-random verification
- Collaboration with cross-functional teams
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, ComputerScience, a related field, or equivalent practical experience.
- 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog .
- Experience developing and maintaining verification testbenches, test cases,and test environments.
Preferred qualifications:
- Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- Experience with low power, debug, Gate Level Simulation (GLS), formal verification.
- Experience in driving cross functional teams for quality tape-outs
- Experience leading design verification of IPs, successfully delivered to many SoCs.
- Experience in driving or owning Sub system level verification and navigating the dependencies with Stakeholders.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities
- Plan the verification of digital design blocks at Sub System level by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs with SVA and industry leading formal tools.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Participate with architecture, design teams, Sival and Software (SW) teams in defining the overall verification strategy of our SoCs.
- Be the primary point of contact for functional verification of the IP for cross-functional teams.
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