Senior Design Verification Engineer, Silicon

This Senior Design Verification Engineer role at Google involves planning and executing the verification of digital design blocks at the subsystem level. Responsibilities include creating and enhancing verification environments using SystemVerilog and UVM, debugging tests with design engineers, and collaborating with cross-functional teams (architecture, design, Sival, and software) to define SoC verification strategies. The ideal candidate will have 8+ years of experience with verification methodologies and languages like UVM and SystemVerilog, experience developing testbenches and test cases, and strong debugging skills. The role requires proficiency in constrained-random verification and potentially formal verification methods. The engineer will be the primary contact for functional verification of IPs across teams and will contribute to delivering high-quality, performant hardware solutions for Google's products.