Senior Member of Technical Staff
Job Summary
Job Description
Own the implementation of block-level subcomponents and their physical integration into a system-on-a-chip (SoC). The design cycle starts with synthesis of Verilog RTL into a Gate Level Description (Verilog netlist), followed by Place and Route (PnR) to produce a manufacturable database (GDS) meeting performance, power, and area specifications. Optimize floor plans for intellectual property cores and subsystems to achieve the smallest footprint area while satisfying electrical integrity. Generate physical and timing constraints, design and analyze high-frequency clock distribution networks, and implement high-performance interfaces. Analyze and close timing by making design changes and fine-tuning critical paths. Run physical verification and fix issues to satisfy foundry design rules. Contribute to PnR flow automation by writing code in scripting languages.
Must have:
- Owned E-core CPU partitions/blocks through PnR flow to GDS.
- Analyzed and closed timing with design changes.
- Optimized floor plans for small footprint areas.
- Performed physical/timing constraints for sub-blocks.
- Designed/analyzed high-frequency clock distribution networks.
- Owned flow updates and contributed to PnR automation.
- Worked on full chip timing analysis and closure.
- Generated ECOs and timing models.
Job Details
Own the implementation of block level subcomponents and their physical integration into the
top level of a system-on-a-chip (SoC). The design cycle will start with synthesis of various
hierarchies to translate a High Level Description Language view of the functionality (Verilog
RTL) into a Gate Level Description (Verilog netlist). Take the netlist through the various steps
of a Place and Route flow (PnR) to produce manufacturable database (GDS) that meet all the
requirements of performance, power, and area specifications of the final product. Optimize floor
plans to integrate intellectual property cores and subsystems from internal groups and external
partners to achieve the smallest footprint area while satisfying all electrical integrity
requirements. Generate physical and timing constraints for sub-block implementation. Design,
implement, and analyze high frequency clock distribution networks at the top and block level to
enable communication between synchronous elements. Design, implement, and analyze high
performance interfaces between subsystems of the SoC for high speed communication. Analyze
and close timing by implementing design changes and fine-tuning of critical timing paths to
ensure the part operates at the target frequency. Run physical verification and implement fixes
to satisfy the design rules established by the chip foundry. Contribute to the automation of the
PnR flow by writing code in industry standard scripting languages to add customization and
collect metrics.
Education:
- Master’s or foreign equivalent in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field
Experience:
- 3 years of experience in job offered or related occupation.
Special Requirements: Must have at least 1 year of prior work experience in each of the following
- Owned partitions/blocks of a E-core CPU and took it through the various steps of a Place and Route flow (PnR) to produce manufacturable database (GDS) that meet all the requirements of performance, power, and area specifications of the final product.
- Analyzing and closing timing by implementing design changes and fine-tuning of critical timing paths to ensure the part operates at the target frequency.
- Optimizing floor plans to achieve the smallest footprint area of a given block (2M+ to 4M+ gates) while satisfying all electrical integrity requirements.
- Performing physical (pin placement) and timing constraints for sub-block implementation. Designing, analyzing and implementing high frequency clock distribution networks at the block level.
- Owning flow updates and contributing to the automation of the PnR flow by writing code in industry standard scripting languages to add customization and collect metrics.
- Working on full chip timing analysis and closure, including performing distributed timing analysis, ECO generation and timing model generation for hand off to SOC teams.
**Telecommuting allowed for this position**
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