Senior Standard cell design engineer

Rivos is seeking an experienced and highly motivated Senior Custom Standard Cell Design Engineer to join our team. In this role, you will play a critical part in developing state-of-the-art custom standard cells for our most advanced FinFET and GAA process nodes. You'll take on a leadership role in the technical direction of projects, driving innovation and mentoring junior team members. Your work will directly impact the performance, power, and area (PPA) of our core designs, making a significant contribution to our next-generation products. This position requires not only deep technical expertise but also the ability to collaborate effectively across multi-disciplinary teams.

What You'll Do:

• Lead Technical Design: Own the end-to-end design and delivery of high-performance custom standard cells, including complex sequential, clock gating, and power management cells.
• Innovate & Optimize: Drive the design of new and innovative circuit architectures to push the boundaries of performance and power efficiency at advanced process nodes (N3/N5 and beyond).
• Mentor & Guide: Provide technical leadership and mentorship to junior engineers, fostering a culture of knowledge sharing and continuous improvement.
• Collaborate Cross-Functionally: Work closely with physical design, layout, and CAD teams to define requirements, optimize designs for PPA, and ensure seamless integration into the chip design flow.
• Validate & Qualify: Perform advanced circuit analysis, reliability checks, and SPICE simulations to validate designs across various corners and ensure compliance with all reliability standards (EM/IR, ESD, Latch-up).
• Improve Methodologies: Proactively identify and implement improvements to design methodologies, tools, and flows to enhance team efficiency and productivity.

What You Bring:

• Experience: 8+ years of relevant experience in custom standard cell design on advanced FinFET nodes. Experience with N3/N5 nodes is highly preferred.
• Technical Expertise:
• Deep understanding of transistor-level circuit design, including static, dynamic, and state-retaining elements (latches, flops).
• In-depth knowledge of CMOS device physics and the challenges of deep sub-micron design, including variation and reliability issues.
• Proven ability to optimize circuit designs for superior PPA.
• Hands-on experience with industry-standard EDA tools for schematic entry, simulation, and characterization.
• Advanced scripting skills in languages like Python, TCL, and Perl for design automation and data analysis.
• Excellent problem-solving and analytical skills with a strong attention to detail.
• Proven ability to provide technical leadership and guidance on complex projects.
• Strong communication and collaboration skills to work effectively with cross-functional teams.