Senior Verification Engineer
Job Summary
Job Description
- 5-8 years of experience
- Good verification skills (Verilog, SystemVerilog)
- Strong UVM methodology knowledge
- AMBA protocols (AXI, AHB, APB)
- Digital design fundamentals
- Scripting (Perl, TCL, Make, shell)
- Good protocol knowledge
- Exposure to Arm-based SOC
- Experience with any other scripting language
3 skills required
Job Details
Project description
We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems.
At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way.
Responsibilities
Verification of processor-based subsystem :: (Running /debugging testcases).
Skills
Must have
5-8y exp
Good verification skills (Verilog, system Verilog).
Strong Knowledge of UVM methodology, with hands on experience of coding testbenches. with Good debug skills.
AMBA
(AXI, AHB, APB)
Good to have protocol knowledge
Exposure to Arm based SOC preferred but not a must
Well versed with digital design fundamentals
Scripting
perl, tcl, Make, shell scripting
Nice to have
Experience with any other scripting language is a plus
Other
Languages
English: B2 Upper Intermediate
Seniority
Lead
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