Senior Verification Engineer

5-8y exp

Good verification skills (Verilog, system Verilog).

Strong Knowledge of UVM methodology, with hands on experience of coding testbenches. with Good debug skills.

AMBA

(AXI, AHB, APB)

Good to have protocol knowledge

Exposure to Arm based SOC preferred but not a must

Well versed with digital design fundamentals

Scripting

perl, tcl, Make, shell scripting

Experience with any other scripting language is a plus