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Silicon Digital Design Engineer

Silicon Digital Design Engineer

1 Month ago • All levels • Research & Development

About the job

4 skills required for this role

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python

perl

innovation

cross-functional

Job Description

This role involves RTL design development of security IP and subsystems for Google's direct-to-consumer products. Responsibilities include micro-architecture design, RTL coding, constraint definition, IP release flows, PPA optimizations, test planning, and collaboration on coverage reviews. The engineer will work on imaging and video codecs and utilize RTL QC tools like Lint, CDC, and VCLP for debugging and improvement. Collaboration with cross-functional teams (verification, DFT, physical design, emulation, software) is crucial for design decisions and project status updates. The ideal candidate possesses expertise in digital logic design, RTL design concepts (Verilog/SystemVerilog), logic synthesis, low-power design techniques, and scripting languages (Perl/Python).

Must have:

RTL design (Verilog/SystemVerilog)
Logic synthesis & optimization
Low-power design techniques
Scripting (Perl/Python)
ASIC design methodologies

Good to have:

Master's/PhD in EE/CS
Process Cores knowledge
Cross-domain understanding
Proficiency with ASIC front quality checks
Micro-architecture design

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
Experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
Experience with logic synthesis techniques to optimize RTL code, performance and power, and low-power design techniques.
Experience with a scripting language such as Perl or Python.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering or Computer Science.
Knowledge in Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, or PinMux.
Understanding of cross-domain involving domain validation, design for testing, physical design, and software.
Proficiency with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation).

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be responsible for Register-Transfer Level (RTL) design development of security IP and subsystems including Micro architecture, RTL coding, definition, constraints, IP release flows, Power Performance Area (PPA) optimizations, test planning collaboration, coverage reviews and closure for quality and optimized security designs. You will be involved in Micro-Arch and RTL coding for imaging and video codecs - IPs and subsystems. You will also contribute to improvements by debugging and using different RTL QC tools like Lint, CDC, or VCLP.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

Work with ASIC RTL Engineers on sub-system and chip-level integration activities including plan tasks, hold code and design reviews, and contribute on sub-system/chip-level integration.
Interact closely with the Architecture team and develop implementation strategies to meet quality, schedule, and power performance and area for sub-system/chip-level integration.
Interact closely with the Subsystem team and plan SOC milestones, plan quality checks as part of SOC milestones, and guide subsystem teams with SOC level requirements (e.g., IPXACT, CSR, Lint, CDC, SDC, UPF, etc.).
Work closely with the cross-functional team of verification, design for test, physical design, emulation, and software teams to make design decisions and represent project status throughout the development process.

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.