Silicon Emulation Engineer

We are seeking full-time SOC Emulation engineers for various aspects of emulation, including functional, performance, microarchitecture, and debug, from subsystem to multi-chip levels. This role involves developing Emulation and FPGA based prototyping systems for SOC projects. You will collaborate with architecture, design, verification, and software/firmware teams to bring up emulation models and develop capabilities for functional verification, performance analysis, software/firmware bringup, running realistic workloads, power estimation, and hybrid-simulation. Responsibilities include creating and supporting emulation models from RTL, driving SOC bringup on emulation platforms, debugging test failures, and developing compile and runtime flows. You will also develop capabilities to run tests on emulators, assist in bring-up processes, work with tool vendors, and contribute to methodology and automation improvements.

Must Have

• Digital logic design knowledge
• CPU/SOC architecture and microarchitecture knowledge
• Verilog/SystemVerilog experience
• C/C++ experience
• Verification methodologies and tools knowledge
• Problem solving skills
• Written and verbal communication skills
• Organization skills
• Self-motivated

Good to Have

• Experience with Palladium, Zebu, Veloce, Protium, or HAPS
• QEmu or other software simulators experience
• Simulation acceleration experience
• Performance analysis/debug techniques experience
• Scripting languages like Python, TCL experience
• Ability to work in a team
• Ability to be productive under aggressive schedules

• Create and support emulation models from RTL. Drive SOC bringup on emulation platforms, debug test failures and simulation/emulation mismatches.
• Develop compile and runtime flows to support various emulation usage models such as functional verification, hybrid simulation, post-si debug, power and software/firmware enablement.
• Develop capabilities to run tests on the emulators and assist in bring-up processes from RTL prototyping through post-silicon validation.
• Work with Tool vendors to drive the requirements and resolve any tool issues.
• Drive and Contribute to the methodology and automation improvements to improve Emulation efficiency and value addition.

• In-depth knowledge of digital logic design, CPU/SOC architecture and microarchitecture, and industry standard interfaces and memory subsystems.
• Experienced level knowledge of Verilog/SystemVerilog.
• Experienced level knowledge C/C++.Relevant knowledge of verification methodologies and tools such as simulators, waveform viewers, build and run automation.
• Experience with Palladium, Zebu, Veloce, Protium or HAPS.
• Experience with QEmu or other software simulators is a plus.
• Experience in simulation acceleration using transactors or vendors provided accelerated verification IP is a plus.
• Experience in performance analysis/debug techniques.
• Excellent knowledge of one of the scripting languages such as Python, TCL is a plus.
• Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
• Ability to work well in a team and be productive under aggressive schedules.

• PhD, Master’s Degree or Bachelor’s Degree in technical subject area.