SOC Design Verification Staff Engineer

4 Months ago • 3-5 Years

Software Development & Engineering

Job Description

As a DV Engineer, you will architect verification strategies for complex auto, compute, mobile, XR-VR, and IoT SOCs. Responsibilities include setting up methodologies, developing test plans, and ensuring designs meet quality standards. You will participate in architecture/product definition. This role involves defining verification architecture, creating test plans, building verification environments, and verifying subsystems and full SOCs using advanced methodologies. You will build agents and checkers, write test plans from design architecture specs, develop test plans to verify low power aspects across all verification modes, and achieve coverage goals. Also, assist in silicon bring-up, debug, and bring-up activities.

Good To Have:

Experience with PSS or higher-level test construction languages.
Working knowledge of GLS, PAGLS and scripting languages such as Perl and Python.
Knowledge of one or more of Multimedia design blocks.
Knowledge of one or more of peripheral blocks verification.

Must Have:

Strong fundamentals in digital ASIC verification.
Experience in IP/SS/SoC level verification.
Familiarity with system level HW and SW debug techniques.
Strong System Verilog/UVM based verification skills.
Working knowledge of Interconnect architecture and Bus protocols.

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Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a DV Engineer with a focus on SOC design verification, you will work to understand the internal requirements and complexities of our highly complex auto, compute, mobile, XR-VR, IoT SOCs and architect the required verification strategy. You will help set up methodologies, develop test plans, and verify that the design meets the highest quality standards. We believe in early involvement of DV, so you will also participate in architecture/product definition through early involvement in the product life-cycle.

Preferred qualifications

· B.E/B.Tech/M.E/M.Tech in Electronics with 5+ year experience in verification domain.

· Strong fundamentals in digital ASIC verification

· Experience in IP/SS/SoC level verification of medium to high complexity design

· Familiarity with system level HW and SW Debug techniques and Verification requirements

· A good understanding of the complete verification life cycle (test plan, testbench through coverage closure)

· Strong System Verilog/UVM based verification skills & Experience with Assertion & coverage-based verification methodology

· Experience w/ PSS or higher-level test construction languages is an added advantage

· Working knowledge of Interconnect architecture and Bus protocols like AMBA - ACE/CHI/AXI

· Good understanding of low power design techniques

· Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells.

· Experience with UPF/CPF based power aware verification.

· Working knowledge of GLS , PAGLS and scripting languages such as Perl, Python is a plus

· Prior work on NoC/Interconnects end to end verification with solid understanding on to Bus protocols, Coherency, Performance, Latency, clock gating etc.

· Knowledge of one or more of Multimedia design blocks such as Display/Camera/Video/GFx

· Knowledge of one or more of peripheral blocks verification such as PCIe/USB/UFS/I3C

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.Roles and Responsibilities

· Define verification architecture, develop test plans and build verification environment

· Work with design team to understand design intent and bring up verification plans and schedules

· Verify Subsystems and Full SoC using advanced verification methodologies

· Build agents and checkers from scratch. Perform and write test plan from design architecture specs and/or protocol standard

· Develop test plan to verify all low power aspects across all modes of verification – RTL, PA-RTL, PA-GLS and Formal

· Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging UPF and RTL and achieving all coverage goals

· Assist in silicon bring-up, debug and bring-up activities

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

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