SOC Physical Design Engineer

rivos

| Santa Clara, California, United States (Hybrid) | Full Time | 51 months ago
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Job Summary

Positions are open for full-time and co-op/internship in the areas of SOC physical implementation from unit level to chip level, involving all aspects of physical design functions such as P&R, timing, floorplan, clocking, electrical analysis, and power. Responsibilities include owning block level design from RTL-to-GDSII, driving synthesis, floor-planning, place & route, timing closure, and signoff. Work with Micro-architects for feasibility studies and PPA tradeoffs, develop physical design methodologies, and work with a multi-functional team to implement and validate physical design by running all signoff flows.

Must Have

  • Own block level design from RTL-to-GDSII
  • Drive synthesis, floor-planning, P&R, timing closure, signoff
  • Perform feasibility studies & PPA tradeoffs
  • Develop physical design methodologies
  • Run signoff flows (Timing, Power, EM/IR, PDV)
  • Knowledge of synthesis, place & route, analysis tools
  • Familiarity with logic & physical design principles
  • Scripting in Unix, Perl, Python, TCL
  • Knowledge of Verilog and SystemVerilog
  • Excellent problem-solving & communication skills
  • Ability to work in a team under aggressive schedules

Good to Have

  • Experience in deep sub-micron technologies
  • Good understanding of device physics

Job Description

Positions are open for full-time and co-op/internship in the areas of SOC physical implementation from unit level to chip level, involving all aspects of physical design functions such as P&R, timing, floorplan, clocking, electrical analysis, and power.

Responsibilities

  • Own block level design from RTL-to-GDSII and drive synthesis, floor-planning, place & route, timing closure, and signoff.
  • Work extensively with Micro-architects to perform feasibility studies and explore performance, power & area (PPA) tradeoffs for design closure.
  • Develop physical design methodologies and customize recipes across various implementation steps to optimize PPA.
  • Work with a multi-functional engineering team to implement and validate physical design by running all signoff flows such as Timing, Power, EM/IR, PDV.

Requirements

  • Knowledge using synthesis, place & route, analysis and verification CAD tools.
  • Familiarity with logic & physical design principles to drive low-power & higher-performance designs.
  • Knowledge of scripting in some of these languages: Unix, Perl, Python, and TCL.
  • Good understanding of device physics and experience in deep sub-micron technologiesKnowledge of Verilog and SystemVerilog.
  • Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
  • Ability to work well in a team and be productive under aggressive schedules.

Education and Experience

  • PhD, Master’s Degree or Bachelor’s Degree in technical subject area.

6 Skills Required For This Role

Cad Computer Aided Design Unity Unix Level Design Python Perl