SOC Physical Design Engineer

Positions are open for full-time and co-op/internship in the areas of SOC physical implementation from unit level to chip level, involving all aspects of physical design functions such as P&R, timing, floorplan, clocking, electrical analysis, and power. Responsibilities include owning block level design from RTL-to-GDSII, driving synthesis, floor-planning, place & route, timing closure, and signoff. Work with Micro-architects for feasibility studies and PPA tradeoffs, develop physical design methodologies, and work with a multi-functional team to implement and validate physical design by running all signoff flows.