SOC Static Timing Analysis Engineer - Full Time

1 Week ago • All levels

About the job

Summary_{By Outscal}

Join a cutting-edge and well-funded hardware startup in Silicon Valley as a Silicon STA Engineer. Our mission is to reimagine silicon and create Risc-V based computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

Responsibilities

Block level and/or full chip timing analysis throughout the life cycle of a project, from early investigation to final implementation and tapeout
Develop our timing methodology and infrastructure to support the timing flow from RTL synthesis to implementation and timing closure
Work with architects and logic designers to generate block and full chip timing constraints
Work with system and technology teams to define analysis scenarios and margining strategies
Develop a rigorous and comprehensive signoff methodology to guarantee high quality robust silicon
Partner with physical design teams to close and sign off the designs

Requirements

Hands-on experience in ASIC timing constraints generation and timing closure
Expertise and advanced knowledge of industry standard timing EDA tools
Deep understanding and experience in timing closure of various functional and test modes
Expertise in timing convergence issues associated with deep-sub micron processes (crosstalk delay, noise glitch, POCV, IR-STA)
Proficient in scripting languages (csh/bash, TCL and Python)
Ability and taste for solving complex problems, efficient written and verbal communication, excellent organization skills
Self starter and highly motivated
Ability to work cross-functionally with various teams and be productive under aggressive schedules

undefined