Job Description
We are seeking talented Application Engineers for physical design in Cadence Korea. You will be responsible for physical design implementation projects, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification, EM/IR signoff, and DFM Closure. The role involves working on challenging low power and high-speed designs at the latest technology nodes and participating in next-generation physical design methodology and flow development. Candidates should have solid knowledge of ASIC design flow, hierarchical physical design strategies, deep sub-micron technology issues, Low Power Design, DFT, static timing analysis, and various verification techniques.
Must Have:
- Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis.
- Ensure timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
- Participate in or lead next generation physical design, methodology and flow development.
- Experience with ASIC design flow, hierarchical physical design strategies, and deep sub-micron technology issues.
- Solid knowledge of Low Power Design, DFT, static timing analysis and closure, data skew balancing, duty cycle adjustment.
- Proficiency in EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM and P&R.
- Ability to assume responsibility for a variety of technical tasks and to work independently.
- Ability to be hands-on at all levels of design, with the ability to verify, test, and characterize own designs.
- Good English communication skills.
- Job Description
- We are seeking talented Application Engineers dedicated for physical design in Cadence Korea. You will be responsible for the physical design implementation projects.
- The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
- The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed designs at the latest technology nodes.
- The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development.
- Additional Job Description
- Experienced with ASIC design flow, hierarchical physical design strategies, methodologies, and understand deep sub-micron technology issues.
- Solid knowledge on Low Power Design, DFT, static timing analysis and closure, data skew balancing, duty cycle adjustment, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM and P&R.
- Able to assume responsibility for a variety of technical tasks and to work independently
- Able to be hands-on at all levels of design, with the ability to verify, test, and characterize own designs
- Self-motivated, able to work as a team player, and good English communication skills
- The candidate will work closely with RTL design team to ensure successful tapeouts.
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