Sr. Silicon Design Engineer

12 Months ago • 5-7 Years

Job Summary

Job Description

Senior Silicon Design Engineer for AMD focusing on physical design, RTL to GDS2 flow, and experience with Synopsys, Cadence & Mentor tools.

Must have:

Physical Design
RTL to GDS2
Synopsys Cadence
Mentor Tools

Good to have:

ASIC Designs
SAPR of RTL
Automated Design
Floorplanning

Perks:

AMD Culture
Next-Gen Computing

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Job Details

Overview:

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_

Responsibilities:

SENIOR SILICON DESIGN ENGINEER

THE ROLE:

We are looking for an adaptive, self-motivative Physical Design Engineer to join our growing team. The position will involve working with a highly experienced physical design team and is responsible for delivering the physical design of blocks to meet challenging PPA goals and other design requirements for AMD next generation chips on cutting edge technology.

THE PERSON:

Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player.

KEY RESPONSIBILITIES:

Implementing RTL to GDS2 flow
Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence
Handling different PNR tools from various vendors - Synopsys Cadence & Mentor.

PREFERRED EXPERIENCE:

5-7 years of professional experience in physical design, preferably ASIC designs.
Experience in automated SAPR of RTL blocks for high speed datapath and control logic applications.
Experience in automated design flows for clock tree synthesis, clock and power gating techniques, design optimization for improved timing/power/area, and design cycle time reduction.
Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery
Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
Versatility with scripts to automate design flow.
Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
Strong analytical/problem solving skills and pronounced attention to details

ACADEMIC CREDENTIALS:

Bachelors or Masters degree in computer engineering/Electrical Engineering

#LI-SR4

Qualifications:

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.