Staff Analog Mixed-Signal Design Engineer

Your Team, Your Impact

As an Analog IC Design Staff Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a small team of selected employees making a big impact on this organization. Additionally, Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects.

What You Can Expect

• Design and develop high-speed and low-power analog mixed-signal circuits in advanced CMOS technologies, with a focus on SerDes (Serializer/Deserializer) die-to-die communication and high-speed wireline design.
• Design of analog mixed-signal blocks such as: ADCs, DACs, Regulators, Clock Generation and Distribution, DLLs, Custom high-speed digital circuits, CTLE, VGA, and TX Drivers.
• Supervise and guide layout activities to ensure design accuracy and performance.
• Utilize state-of-the-art EDA tools for design automation and verification.
• Prepare and maintain detailed documentation of design processes and results.
• Prepare and participate in design reviews to ensure design quality and compliance with project requirements.

What We're Looking For

• Solid analog mixed signal design knowledge in advanced CMOS technologies, including trade-offs and optimization techniques for performance and power efficiency.
• 4+ years of demonstrated experience in analog mixed-signal design, specifically in one or more of the following areas: ADC, DAC, voltage regulators, clock generation and distribution circuits, DLLs, custom high-speed digital circuits, CTLE, VGA, and TX drivers.
• Ability to identify, analyze, and resolve design issues, ensuring robust and reliable circuit performance.
• Experience in overseeing layout engineers, providing guidance on best practices, and ensuring that layout designs meet performance, area, and reliability requirements.
• Good understanding of CMOS process technology, device physics, and the impact of process variations on circuit performance.
• Fluent in using electronic design automation (EDA) tools for schematic capture, simulation, layout, and verification, such as Cadence, Synopsys, or Mentor Graphics.

Expected Base Pay Range (USD)

118,900 - 178,100, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.