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Capgemini

DESIGN VERIFICATION |9 TO 12YEARS| BENGALURU & HYDERABAD

Pega CI/CD | 14 to 15 Years | Gurugram

L3 Developer-Parwana Shahdi

Seeking experienced Design Verification Engineers to lead verification of IPs and SoCs. Must have expertise in Verilog, SV, UVM/OVM, IP Verification, and SoC Verification.  Strong scripting skills in Perl, Python, or Shell are essential. Experience with ARM-based SoC verification and GLS is a plus.

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 Job Description <ul><li>You will be part of the team verifying IPs and SoCs leading to first Si success. </li><li>Manage and lead a team of Verification engineers</li><li>IP verification is coverage driven using latest industry standard methodologies and HVLs. </li><li>Work involves defining verification strategy, writing test plans, developing efficient test benches and test cases. </li><li>Code coverage, Functional coverage and assertions are desired. </li><li>ARM based SoC verification experience is an added advantage. </li><li>Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc. is a great plus.</li><li>Multiple positions with emphasis on AMS and Power aware verification.</li><li>Should have worked on GLS. </li></ul>
Primary Skills <ul><li>Verilog, SV, UVM/OVM, IP Verification, SoC Verification, scripting – Perl, Python, Shell, and Tcl. </li></ul>
Secondary Skills <ul><li>Test bench / model / VIP development, Functional coverage, GLS, LEC, Emulation, AMS, ARM, Protocols AHB/AXI/APB, Ethernet, USB, PCIe, I2C, SPI, CAN, Mipi CSI/DSI, LPDDR</li></ul>

 
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