Design Verification - Staff Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, a place to thrive, learn, and lead.

Your Team, Your Impact

The Connectivity Business Unit at Marvell focuses on developing a broad portfolio of connectivity product lines. This includes Copper PHY, High-Speed Connectivity (HSC), Optical DSP (ODSP), Coherent DSP (CDSP), and Broadband Access (BBA) solutions. The unit is dedicated to providing high-speed connectivity solutions for various applications, including data centers, cloud, carrier, and automotive sectors

What You Can Expect

• Playing as a technical expert and contributing to the definition of project architecture.
• Providing technical expertise and guidance to the Design Verification (DV) team, including test plan reviews, testbench architecture reviews, and overall technical support.
• Collaborating with Design and Verification teams to develop and execute comprehensive verification strategies.
• Defining and implementing verification plans for Serdes/PHY chip designs.
• Creating and maintaining testbenches using industry-standard verification tools and methodologies.
• Performing functional and performance verification of complex digital designs.
• Working closely with digital design, analog, and architecture teams to identify and resolve design issues.
• Analyzing and debugging simulation failures, and providing detailed reports on verification results.
• Mentoring and guiding junior verification engineers.
• Modeling and verifying DSP design circuits using MATLAB and/or co-simulation (System-C/C++ and System Verilog).
• Ensuring verification sign-off for various chips, guaranteeing timely release with exceptional quality.

What We're Looking For

• Education: BS/MS/PhD in Electrical Engineering, Computer Engineering, Electronics and Telecommunications Engineering, or a related field.
• Technical Skills:
• Proficiency in verification languages such as SystemVerilog, UVM, and scripting languages (Python, Perl, etc.).
• Strong understanding of ASIC design flow, digital design, and verification methodologies.
• Experience with industry-standard EDA tools (e.g., Cadence, Synopsys, Mentor Graphics).
• Strong mathematical skills and experience with Digital Signal Processing (DSP), including DSP modeling in MATLAB.
• Problem-Solving: Strong problem-solving and debugging skills.
• Communication: Fluent in English with excellent communication skills.
• Preferred Qualifications:
• Experience with high-speed Serdes/PHY interfaces design and design verification.
• Ability to understand chip-level, subsystems, and complex blocks to define the strategy and scope of Design Verification.
• Capability to define and develop testbenches for chip-level, subsystems, and complex blocks using advanced verification methodologies (e.g., Universal Verification Methodology (UVM)).
• Experience in chip-level verification and strong knowledge of test-plan generation.
• Ability to contribute to the definition of project architecture.

Additional Compensation and Benefit Elements

• Competitive salary, plus 13th-month salary and performance-based bonus
• RSUs (Restricted Stock Units) for new joiners and on-going annually
• Premium health & accident insurance for you and your family (spouse and children)
• Annual medical check-up at a designated hospital arranged by Marvell
• Generous paid leave policies: 15 annual leave days, 3 Recharge periods per year (company-wide off-work from Friday to Monday), 5 paid sick leave days, 3 days of volunteer time-off and 11 public holidays
• Exciting Employee Events: Participate in fun activities throughout the year such as team birthdays, sports tournaments, company trips, mid-autumn, appreciation week, charity, health seminars, year-end party, and more.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.