RTL Design(DSP)-Sr Lead
Job Summary
Job Description
- 3 to 15 years of practical experience in RTL development (VHDL and/or Verilog)
- Functional and structural RTL design
- Design partitioning
- Simulation and regression
- Collaboration with design verification team
- Familiarity with simulation systems (e.g., Modelsim, VCS)
- Experience with synthesis tools (e.g., Design Compile)
- Experience with static timing tools (e.g., Prime Time)
- Knowledge of Linting tools, CDC tools, UPF, code coverage, System Verilog Assertion
- Develop RTL for multiple logic blocks of a DSP core
- Run various frontend tools to check for linting, clock domain crossing, synthesis, etc.
- Work with physical design team on design constrain and timing closure
- Work with power team on power optimization
- Work with verification team to collaborate on test plan, coverage plan, and coverage closure
- Strong processor architecture knowledge
- Microarchitecture implementation
- Microprocessor integration
- Low power design
- World-class health benefit options providing world-class coverage to employees and their eligible dependents
- Programs designed to help employees build and prepare for a financially secure future
- Self and family resources to build emotional/mental strength and resilience, as well as define purpose
- Wellbeing programs and resources to help employees Live+Well and Work+Well
- Continuous learning and development programs
- Tuition reimbursement
- Mentorships
3 skills required
Job Details
Job Posting Date
2025-09-10
Company:
Qualcomm India Private Limited
Job Area:
Engineering Group, Engineering Group > Hardware Engineering
General Summary:
This position is for RTL designer role in DSP processor team. The position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful candidate will possess detailed understanding of RTL design, synthesis, static timing analysis, formal verification, PLDRC, clock domain crossing, and low power techniques. Knowledge and experience of microprocessor integration is a definite advantage.
Skills/Experience
Must have 3 to 15 years of practical experience with details of RTL development (VHDL and/or Verilog) including:
functional and structural RTL design, design partitioning,
simulation and regression, collaboration with design verification team. Must have good familiarity with latest RTL languages and tools, including: simulation systems (e.g. Modelsim, VCS), synthesis tools (e.g. Design Compile), static timing tools (e.g. Prime Time), Linting tools, CDC tools, UPF, code coverage, System Verilog Assertion, etc.
Experience with the following area is highly desirable:
- Strong processor architecture knowledge
- Microarchitecture implementation
- Microprocessor integration
- Low power design
Responsibilities
Develop RTL for multiple logic blocks of a DSP core
Run various frontend tools to check for linting, clock domain crossing, synthesis, etc.
Work with physical design team on design constrain and timing closure
Work with power team on power optimization
Work with verification team to collaborate on test plan, coverage plan, and coverage closure
Minimum Qualifications:
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
- Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
- PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
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