Senior Staff Static Timing Analysis & Physical Design Engineer

Your Team, Your Impact

The Marvell Physical Design team is located in our Boise, ID office, and has a long history of successful design tapeouts in advanced process nodes. Our team is made up of both newer and more experienced engineers with a broad depth of static timing analysis and physical design engineering experience. Being a part of our team will give you a chance to work on many different aspects of the chip design process, while working alongside some of the best engineers in the industry. In this unique role, you’ll have the opportunity to work on both the timing analysis and methodology for future designs of our next-generation, high-performance processor and data center chips in a leading-edge CMOS process technology.

What You Can Expect

This role is based in the Marvell office in Boise, ID. You will work with both local and global STA team members on the timing analysis and timing closure of complex chips, as well as the methodology to enable an efficient and robust design process.

Key responsibilities include:

• Work with teams across various disciplines such as PD/Digital/RTL/Analog to ensure design convergence and integration in a timely manner.
• Perform Static Timing Analysis and design timing convergence and closure on multi-voltage designs using industry standard EDA tools (PrimeTime preferred).
• Work with RTL design teams to drive assembly and design closure.
• Collaborate with physical design engineers to drive designs to timing closure.
• Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes.
• Write scripts in Shell, Python, and TCL to extract data and achieve productivity enhancements through automation.

What We're Looking For

Basic Qualifications:

• Bachelor's Degree in Electrical/Computer Engineering plus 3-5 years of related experience, OR a Master's Degree in Electrical/Computer Engineering with 2-3 years related experience.
• Expertise in full-chip & sub-hierarchy integration.
• Experience integrating and taping out large designs utilizing a digital design environment.
• Good understanding of RTL to GDS flows and methodology.
• Good scripting skills in TCL/Python.
• Knowledge of Verilog.

Preferred Qualifications:

• Static Timing Analysis familiarity or experience.
• Expertise in Static Timing Analysis using industry-standard STA tools (PrimeTime preferred).
• Experience driving timing closure and taping out large designs utilizing a digital design environment.
• Experience with advanced Clock Tree Synthesis and Analysis techniques.
• Experience closing timing in a Tessent DFT based design is a plus.
• Experience with Cadence Innovus.
• Experience with PrimeTime.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.