STA Application Engineer
Job Description
- Hands-on experience with Cadence design tools (Tempus, ETS) or equivalent.
- Successful completion of chip tapeout (40nm/below and/or hierarchical implementation).
- Experience in advance node timing signoff and RC extraction.
- Timing ECO experience.
- Ability to work on-site at customer premises and meet deadlines.
- Senior-level technical expertise in digital front-end implementation, STA, and Timing ECO.
- Ability to interact with and advise customers.
- Solid background in circuits, electronics, and physics.
- Experience handling large design implementation and architectural tasks independently.
- Proficiency in assessing customer design environments and building solutions with Cadence tools.
- MS degree with 3+ years of experience in electrical engineering or microelectronics.
- Strong verbal and written communication and reporting skills in English.
Position Description:
1) The candidates should be senior in a way that they are not only technical excellent but also mature & able to talk to customers, advise customers as well as other, following team members. This engineer should have excellent design experiences in the digital front end implementation domain: STA / Timing ECO
2) The engineer must have a solid background in circuits, electronics & physics & should be very willing to learn new stuff.
3) Key Accountabilities: Ability to handle large sized design implementation tasks & architectural tasks alone. Ability to assess Customer's Design environment, to understand his application needs & to build new Design environment based on specifications & available Cadence tool technology.
4) Ability to acquire a basic understanding of the (services) business environment of Cadence. Feeling responsible for technical delivery as well as business development & opportunity creation.
5) Behavioral competencies: Teamwork; Customer focus; Accountability; Communication; Leadership; Proactive;
Position Requirements:
Essential Qualifications:
1) MS degree with 3+ years of applicable experience in electrical engineering, microelectronics.
2) Essential that the individual demonstrates strong communication, verbal and written, and reporting skills.
3) Good verbal and written communication skill in English is needed.
Desirable Qualifications:
1) Will have demonstrated hands-on experience and expertise with Cadence design tools (Tempus, ETS ) or equivalent tools, flows and methodologies required to execute a front end design project.
2) Will have demonstrated successful completion of chip tapeout (40nm/and below tapeout and/or hierarchical implementation experience are a real plus) as an individual contributor
3) Is able to work on-site at customer premises and put in long hours when required to meet customer deadline.
4) Experience in advance node timing signoff and RC extraction
5) Timing ECO experience is definitively a plus.
