STA/EMIR IC Lead Solutions Engineer
1 Hour ago • 3 Years +
System Design
Job Description
This role involves leading and executing technical campaigns for Cadence's Tempus-Signoff tool, performing timing and correlation benchmarks, and ensuring the integrity of delivered solutions. The individual will work with R&D on tool features and bug fixes, focusing on physical design aspects like timing analysis, ECO flows, extraction, power, and EMIR. Responsibilities include static timing analysis, advanced OCV/SOCV concepts, and automation using scripting languages.
Must Have:
- Perform Static timing analysis, glitch, noise analysis, extraction using Cadence Signoff tools.
- Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed, Concurrent and Hierarchical STA flows.
- Work efficiently with R&D and customer to enable various timing analysis & ECO flows.
- Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs.
- Work on In-design timing ECO optimizations solutions with basic knowledge of Place and Route, Clock Tree, RC Extraction, power and UPF/CPF concepts.
- Execute and lead Tempus timing signoff campaigns at existing and new customers.
- Automation of flows using scripting languages (Tcl, python).
- Deliver technical trainings and seminars within Cadence and customer sites.
- 5 years experience with Bachelors in Engineering or 3 years experience + Master in related field of VLSI, Semiconductor, Electrical or Computer Engineering.
- Expert in Static Timing Analysis with knowledge of Physical Design and ECO flows, Power, Extraction.
- Good understanding of Cadence Tools & flows like Tempus, Innovus or equivalent.
- Have basic understanding of Place and route, power analysis.
Individual will be leading and executing technical campaigns at various internal and external customers. Perform several timing & correlation benchmarks with Cadence Tempus -Signoff tool. Execute and deliver on timing analysis, ECO flows, Extraction, Power, EMIR and/or physical design and ensure integrity of delivered solutions. Individual should be able to efficiently work with Cadence R&D to enable various tool feature and close tool bug fixes. Work on various aspects of physical design including timing analysis, place and route, extraction, spice etc.
Job Responsibilities:
- Perform Static timing analysis, glitch, noise analysis, extraction using Cadence Signoff tools. Executing and delivering on various aspects of Timing analysis flows, ECO flows, Power/EMIR, CAD tools and methodologies.
- Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed, Concurrent and Hierarchical STA flows.
- Work efficiently with R&D and customer to enable various timing analysis & ECO flows.
- Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs.
- Work on In-design timing ECO optimizations solutions with basic knowledge of Place and Route, Clock Tree, RC Extraction, power and UPF/CPF concepts.
- Execute and lead Tempus timing signoff campaigns at existing and new customers.
- Automation of flows using scripting languages (Tcl, python).
- Deliver technical trainings and seminars within Cadence and customer sites.
Requirement:
- 5 years experience with Bachelors in Engineering or 3 years experience + Master in related field of VLSI, Semiconductor, Electrical or Computer Engineering.
- Expert in Static Timing Analysis with knowledge of Physical Design and ECO flows, Power, Extraction.
- Good understanding of Cadence Tools & flows like Tempus, Innovus or equivalent.
- Have basic understanding of Place and route, power analysis.
Related tools/Keywords; Tempus, PT, STA, Quantus
Set alerts for more jobs like STA/EMIR IC Lead Solutions Engineer
Set alerts for new jobs by Cadence
Set alerts for new System Design jobs in United States
Set alerts for new jobs in United States
Set alerts for System Design (Remote) jobs
