Staff Engineer - STA

46 Minutes ago • 8-14 Years

Job Summary

Job Description

Alphawave Semi is seeking an experienced STA engineer to lead timing convergence of SoCs. Responsibilities include STA setup, convergence, reviews, and sign-off for Multi-Mode and Multi-corner Multi voltage domain designs. The role involves constraint generation & maintenance for Block/SOC for complex hierarchical designs, timing analysis, and timing closure. The engineer will interact with Design, DFT, IP & PD teams for Timing Convergence, support the Verification team for GLS, guide CTS strategies, manage timing ECO generation, and develop automation scripts. The position reports to the Director - ASIC engineering. The company offers a flexible work environment and a comprehensive benefits package.

Must have:

Experience in full chip synthesis/STA for tape outs.
Experience with block-level and full-chip timing constraints.
Deep understanding of DFT constraints.
Experience with Synthesis & STA on Lower node Technologies
In-depth understanding of Library / Memory / Other collaterals.
Understanding of Ultra Submicron issues and CTS methodologies.
Good knowledge on Timing Budgets.

Good to have:

Knowledge of Perl / TCL / Python scripting language.
Experience with multi voltage designs using CPF/UPF.
Understanding of timing/area/power/complexity tradeoffs.
Experience with power analysis using PTPX.
Understanding of VHDL / Verilog Constructs.
Familiarity with IP level verification.

Perks:

Competitive Compensation Package
Restricted Stock Units (RSUs)
Provisions for advanced education
Medical Insurance and Wellness Benefits
Educational Assistance
Advance Loan Assistance
Office lunch & Snacks Facility

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7 skills required for this role

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python

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team-player

innovation

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talent-acquisition

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Job Details

The Opportunity
We're looking for the Wavemakers of tomorrow.

Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.

What you'll need:

Good understanding of overall design Flow RTL to GDS.
Must have 8- 14 years of experience on signing off the full chip synthesis/STA for tape outs
Hands on Experience on Both Block level and Full chip timing Constraints Development and Management for hierarchical designs.
Deep Understanding of DFT Constraints.
Hand on Synthesis & STA Experience on Lower node Technologies with Synopsys/Cadence Tools.
good understanding of overall ASIC Physical Design/DFT, Tools and implication on Timing Convergence
Must have in-depth understanding of relevant areas of Library / Memory / Other collaterals and dependencies on STA
Must understand Ultra Submicron issues, Variation aware/Aging Aware Design Sign-off Must understand CTS/Other clock Distribution methodologies well.
Good knowledge on Timing Budgets.
Knowledge on Perl / TCL / Python scripting language
Experience on multi voltage designs using CPF/UPF.
Good understanding on timing/area/power/complexity tradeoffs on complex interface design
Hands on experience on power analysis using PTPX
Good understanding of VHDL / Verilog Constructs.
Familiarity with IP level verification and strong RTL debugging capabilities is an added bonus
A, enthusiastic team player who enjoys working with others
Experience troubleshooting issues with users Experience communicating updates and resolutions to customers and other partners complex technical concepts to other design peers in verbal and written form

What You'll Do:

We are looking for experienced STA engineer to lead the timing convergence of the SoCs.Responsibilities include

STA setup, convergence, reviews and sign-off for Multi-Mode and Multi-corner Multi voltage domain designs.
Constraint Generation & Maintenance for Block / SOC for complex hierarchical Designs for all the Modes
Timing analysis, and timing closure at Full chip level while supporting the PD team on Block/SS level timing convergence.
Interaction with Design, DFT, IP&PD teams for Timing Convergence & Resolving Constraint Conflicts.
Support Verification team to enable GLS.
Guide the CTS strategies and provide feedback to Implementation Team.
Manage the timing ECO generation and strategize the implementation methodology.
Develop Automation scripts with-in STA tools for Methodology development.
You will be reporting to Director - ASIC engineering.

'' We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:

Competitive Compensation Package
Restricted Stock Units (RSUs)
Provisions to pursue advanced education from Premium Institute, eLearning content providers
Medical Insurance and a cohort of Wellness Benefits
Educational Assistance
Advance Loan Assistance
Office lunch & Snacks Facility

Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.