Staff STA CAD Engineer

2 Months ago • 2-5 Years • $105,470 PA - $158,000 PA
Software Development & Engineering

Job Description

Marvell is empowering the global data economy. As a key CAD member of Marvell Central Engineering, you will play a leading role in developing next-generation automated design flow and add-on tools. You will have the opportunity to use your extensive design and CAD knowledge to define the whole organization's design methodology and work flow. You will develop, maintain, and lead signoff static timing analysis (STA) and timing ECO flows, contribute to their deployment, and ensure optimal integration within the CAD platform. You will also innovate solutions for design challenges, keep up with tool evolutions, and interface with EDA vendors.
Good To Have:
  • Ability to run SDC linting and constraints checking tools
  • Experience with P&R
  • Experience with EM/IR
  • Experience with EDA tool benchmarks
Must Have:
  • Develop, maintain, and lead signoff STA and timing ECO flows.
  • Contribute to the deployment and support of these flows.
  • Work with the team for optimal integration into the CAD platform.
  • Come up with innovative solutions to design challenges.
  • Keep up with process and tool evolutions.
  • Interface with EDA vendors for optimal tool usage.
  • Hands-on experience in Signoff STA, extraction, and timing ECO flows.
  • Recent experience with Cadence Tempus or Synopsys PT-SI.
  • Solid understanding of timing constraints quality assessment and debug.
  • Solid understanding of timing correlation between tools.
  • Understand timing variation aspects and their impact on analysis.
  • Experience with block-level and chip-level signoff STA.
  • Experience with block and chip-level timing ECOs and feedback.
  • Experience with signoff power analysis and optimization.
  • Ability to handle multi-voltage designs in signoff STA.
  • Knowledge of Place and Route (P&R) and physical impacting.
  • Excellent proficiency in Tcl scripting for flow development.
  • Demonstrate good analysis and problem-solving skills.
  • Be a team player with good communication skills.
Perks:
  • base pay
  • bonus
  • equity
  • flexible time off
  • 401k
  • year-end shutdown
  • floating holidays
  • paid time off to volunteer

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Your Team, Your Impact

Marvell is empowering the global data economy. Whether at the network core or edge, our leadership technologies make it possible for the world’s data to be processed, moved, stored and secured faster and more reliably. With leading intellectual property and deep system-level knowledge, Marvell's infrastructure semiconductor solutions are transforming the cloud, enterprise and automotive markets of tomorrow.

As a key CAD member of Marvell Central Engineering, you will play a leading role in developing next-generation automated design flow and add-on tools. You will have the opportunity to use your extensive design and CAD knowledge to define the whole organization's design methodology and work flow.

What You Can Expect

  • Develop, maintain and lead signoff static timing analysis (STA) and timing ECO flows addressing the needs of Marvell’s various Business Units.
  • Contribute to the deployment and support of these flows.
  • Work in collaboration with the rest of the team to ensure optimal integration inside the overall CAD platform.
  • Come-up with innovative solutions to ever-increasing design challenges.
  • Keep up with process and tool evolutions.
  • Interface with EDA vendors for optimal tool usage.

What We're Looking For

Minimum Qualifications:

  • BS in EE/CS with 3-5 years of hands-on experience, or MS in EE/CS with 2-3 years of hands-on experience, both in Signoff STA, extraction, and timing ECO flows and methodology.
  • Recent experience with either Cadence Tempus or Synopsys PT-SI (experience with both is a plus).
  • Solid understanding of:
  • Timing constraints quality assessment, Timing analysis and debug.
  • Timing Correlation between tools.
  • Solid understanding of timing variation aspects and it’s impact on timing analysis.
  • Block-level and chip-level signoff STA.
  • Block and chip-level timing ECOs and feedback into physical implementation system.
  • Signoff power analysis and optimization.
  • Handling of multi-voltage designs in signoff STA.
  • Knowledge of Place and Route (P&R) especially understanding of physical impacting in implementing timing ECOs.
  • Excellent proficiency in Tcl scripting in the context of flow development.
  • Demonstrate good analysis and problem-solving skills.
  • Team player with good verbal and written communication skills.

Preferred Qualifications:

Ability to run the following tasks is a plus:

  • SDC linting and constraints checking tools
  • P&R
  • EM/IR
  • Experience with EDA tool benchmarks

Expected Base Pay Range (USD)

105,470 - 158,000, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

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