Responsibilities:

• As one member of wireless group, you will
• Create the DV test bench based on design spec from designer;
• Based on design features, create test plan;
• Create test cases according to test plan;
• Generate DV coverage and improve with design;
• Work closely with architecture engineer as well as RTL designer the whole phase to develop new IP.

Requirements:

• Masters’ student in electronic/computer engineering
• Very familiar with uvm and sv language.
• Very familiar with the Verilog HDL language, know VHDL is a plus.
• Test experience on MCU controller design is a plus;
• Very familiar with digital design EDA tools such as DC,PT,Formality;
• 1+ years’ experience on IP simulation and debug process using VCS and Verdi;
• Familiar with the flow of the IC design.
• Strong communication skills