Responsibilities:
• Responsible for leading-edge chip and block level RTL synthesis, logic equivalent check, clock tree synthesis, P&R, STA.
• Responsible for floor-plan, power integrity and physical verifications.
• Tight collaborations with global peer teams from various functions.
Requirements:
• Master in study, major in microelectronics, electronic engineering , computer science or relevant disciplines.
• Knowledge and experience in SoC design, with backend ones being a plus.
• Script coding ability Perl/TCL/Python in Linux/Unix environment.
• Excellent communication skills and collaboration spirit.
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