Job Description
The intern will be responsible for leading-edge chip and block-level RTL synthesis, logic equivalent check, clock tree synthesis, place and route, and static timing analysis. This includes floor planning, power integrity, and physical verification. The role involves close collaboration with global peer teams across various functions. A Master's degree in microelectronics, electronic engineering, computer science, or a related field is required, along with knowledge and experience in SoC design, particularly in backend processes. Proficiency in scripting languages like Perl, TCL, or Python within a Linux/Unix environment is essential, as are excellent communication and collaboration skills.
Good To Have:
- Backend SoC design experience
Must Have:
- Master's degree in microelectronics, electronic engineering, computer science, or related.
- Knowledge of SoC design, backend experience is a plus.
- Scripting ability in Perl/TCL/Python on Linux/Unix.
- Excellent communication and collaboration skills.
- RTL synthesis and static timing analysis.
- Floor-plan, power integrity, and physical verification.
Responsibilities:
• Responsible for leading-edge chip and block level RTL synthesis, logic equivalent check, clock tree synthesis, P&R, STA.
• Responsible for floor-plan, power integrity and physical verifications.
• Tight collaborations with global peer teams from various functions.
Requirements:
• Master in study, major in microelectronics, electronic engineering , computer science or relevant disciplines.
• Knowledge and experience in SoC design, with backend ones being a plus.
• Script coding ability Perl/TCL/Python in Linux/Unix environment.
• Excellent communication skills and collaboration spirit.
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