Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

Job Description

The position involves design verification of next generation modem sub systems (which has MAC, Baseband and RF IP’s involved for latest Wi-Fi protocol including 11ax) with emphasis on verifying and signing off performance and power along with functionality. This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, GLS and Formal techniques. Candidate will require close interactions with Design, SoC , Validation, Synthesis & PD teams for design convergence. Candidate must be able to take ownership of IP/Block/SS verification. He/She will work with design team (both HW and SW) on RTL debug during Pre-silicon HW development phase.

Responsibilities:

• Develop and execute verification plans using SystemVerilog and UVM to validate complex ASIC/FPGA designs.
• Design and implement testbenches and verification environments to ensure functional accuracy and performance.
• Perform Gate-Level Simulations (GLS) to validate designs against their RTL implementations.
• Create and run comprehensive verification scenarios and identify discrepancies between RTL and gate-level simulations.
• Collaborate with design engineers to understand requirements and resolve design issues.
• Debug and troubleshoot complex issues, providing detailed analysis and solutions.
• Document verification processes, methodologies, and results to ensure clarity and reproducibility.
• Participate in design reviews and contribute to improving verification strategies and methodologies.
• Verify and debug low-power design
• Debug SDF Back Annotated Gate Simulations
• Collaborate with cross-functional teams to define and execute gate-level simulation test plans.
• Develop and implement gate-level simulation strategies for complex digital designs.
• Conduct gate-level simulations to verify the functionality and performance of digital designs.
• Work closely with design and verification teams to identify and resolve issues at the gate level.
• Utilize your expertise in SV and UVM to optimize and enhance the gate-level simulation process.
• Ensure compliance with industry standards and best practices in gate-level simulation.
• Develop a comprehensive GLS methodology for the CPU
• Perform gate-level simulations to verify the functionality, performance, and timing of CPU designs.
• Develop and execute comprehensive test plans for gate-level simulations.
• Collaborate with RTL design, verification, and physical design teams to identify and resolve simulation issues.
• Analyze simulation results, debug failures, and propose design improvements.
• Ensure thorough coverage and validation of all critical paths and corner cases.
• Automate simulation workflows to enhance efficiency and reproducibility.
• Assist in the development and maintenance of simulation environments and tools.
• Document simulation methodologies, results, and best practices.
• Understanding of industry-standard protocols and interfaces
• Familiarity with static timing analysis (STA) and power analysis.
• Understanding of power domains and HW programming guide sequences
• Develop test plan to verify all low power states
• Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging UPF and RTL and achieving all coverage goals
• Exploring innovative dynamic or static methodologies by engaging with EDA vendors