Chipset Power Architect, Devices and Services, Silicon
Job Description
- Master's/PhD in relevant field
- ASIC design flow experience
- Low power architecture optimization techniques (multi-Vth, clock/power gating, DVFS)
- 8+ years SoC power modeling & analysis
- SoC architecture and power techniques expertise
- Define power requirements and KPIs
- Drive power optimizations throughout design cycle
Minimum qualifications:
- Bachelor's degree in Electronics or Computer Engineering/Science, or equivalent practical experience.
- 8 years of experience with SoC power modeling and analysis.
- Experience with SOC architecture and power techniques.
Preferred qualifications:
- Master's degree or PhD in Electronics, Computer Engineering, or Computer Science.
- Experience with ASIC design flows.
- Experience with low power architecture and power optimization techniques (e.g., multi Vth/power/voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling).
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.
Responsibilities
- Define power requirements for an SoC to optimize Power-Performance-Area (PPA) under current and thermal constraints.
- Define power KPIs and SoC/IP-level power goals, guide architecture, design, implementation, and software to achieve power goals, and track power throughout the design cycle.
- Propose and drive power optimizations throughout the design process from concept to mass productization.
- Perform algorithm development, modeling, and analysis of various power approaches.
- Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions.
