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Chipset Power Architect, Devices and Services, Silicon

Chipset Power Architect, Devices and Services, Silicon

1 Month ago • 8 Years + • Research & Development • Undisclosed

About the job

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Job Description

This Chipset Power Architect role at Google involves defining power requirements for an SoC, optimizing Power-Performance-Area (PPA), and setting power KPIs. Responsibilities include guiding architecture, design, implementation, and software to meet power goals, proposing and driving power optimizations, performing algorithm development and analysis, and conducting power-performance trade-off analyses. The ideal candidate will have a Bachelor's degree in Electronics or Computer Engineering/Science (Master's or PhD preferred) and 8+ years of experience with SoC power modeling and analysis. Experience with ASIC design flows and low power architecture techniques is highly desirable. The role contributes to the development of custom silicon solutions for Google's consumer products.

Must have:

8+ years SoC power modeling & analysis
SoC architecture and power techniques expertise
Define power requirements and KPIs
Drive power optimizations throughout design cycle

Good to have:

Master's/PhD in relevant field
ASIC design flow experience
Low power architecture optimization techniques (multi-Vth, clock/power gating, DVFS)

Minimum qualifications:

Bachelor's degree in Electronics or Computer Engineering/Science, or equivalent practical experience.
8 years of experience with SoC power modeling and analysis.
Experience with SOC architecture and power techniques.

Preferred qualifications:

Master's degree or PhD in Electronics, Computer Engineering, or Computer Science.
Experience with ASIC design flows.
Experience with low power architecture and power optimization techniques (e.g., multi Vth/power/voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling).

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.

Responsibilities

Define power requirements for an SoC to optimize Power-Performance-Area (PPA) under current and thermal constraints.
Define power KPIs and SoC/IP-level power goals, guide architecture, design, implementation, and software to achieve power goals, and track power throughout the design cycle.
Propose and drive power optimizations throughout the design process from concept to mass productization.
Perform algorithm development, modeling, and analysis of various power approaches.
Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions.

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.