Design Automation Engineer

• Design automation flow support and development
• Parasitic extraction and simulation, abstract and LEF/DEF generation, LVS/ERC checks
• Physical verification runset support and development
• Integration of flows and checks into design cockpits
• Regression testing of flows and verification checks
• Conducting design reviews & creating slides and other associated documentation
• Assisting with integration of IP into SOCs and creating guidelines
• Providing guidance to designers for fixing issues arising from LVS, ERC and LPE errors

Knowledge and Experience required:  

• A good understanding of IP & ASIC design methodologies
• Experience implementing design automation using Cadence Virtuoso for Analog and Mixed-Signal IP development
• Knowledge of various environments and languages – Shell Scripting, Linux development environment, PERL, RUBY, TCL, SKILL/SKILL++, C, C++
• Familiarity with advanced semiconductor process technologies like 3nm, 5nm, 7nm; Design experience is a plus.
• Familiarity with software & design data management systems like git, DesignSync
• Familiarity with common EDA data formats like LEF/DEF, OASIS, openAccess, SPICE/SPECTRE
• Familiarity with EDA verification languages TVF, SVRF, PXL
• Knowledge of various EDA offerings from major EDA suppliers in semiconductor industry for IP and chip design
• The ideal candidate will have wide-ranging experience, with a demonstrated ability to rely on thorough understanding of engineering fundamentals
• The ideal candidate will also have a demonstrated ability to clearly present their work to designers and to non-experts as well
• Working in team environment is a must and everyday interaction with internal customers is part of the job

Education:

• Bachelor’s degree in Electrical Engineering and 8+ years of related experienc or Master’s degree and 6+ years of related experience, or PhD and 3+ years of related experience.