Design Verification Engineer

As a Design Verification Engineer, you will be crucial in guaranteeing flawless first silicon for a segment of the System on a Chip (SoC) or Intellectual Property (IP). Your responsibilities include crafting detailed test and coverage plans grounded in micro-architecture, and developing verification methodologies adaptable for the IP, to ensure a scalable and portable environment. You will be involved in building verification environments, encompassing stimulus, checkers, assertions, trackers, and coverage. Moreover, you'll devise verification plans for all features under your purview, execute these plans, including design bring-up and verification environment setup, enable regression, and debug test failures. You will also contribute to developing block, IP, and SoC level test benches and track progress using bugs and coverage metrics.