Design Verification Engineer

1 Month ago • All levels • Software Development & Engineering • $143,100 PA - $264,200 PA

Job Summary

Job Description

As a Design Verification Engineer, you will be crucial in guaranteeing flawless first silicon for a segment of the System on a Chip (SoC) or Intellectual Property (IP). Your responsibilities include crafting detailed test and coverage plans grounded in micro-architecture, and developing verification methodologies adaptable for the IP, to ensure a scalable and portable environment. You will be involved in building verification environments, encompassing stimulus, checkers, assertions, trackers, and coverage. Moreover, you'll devise verification plans for all features under your purview, execute these plans, including design bring-up and verification environment setup, enable regression, and debug test failures. You will also contribute to developing block, IP, and SoC level test benches and track progress using bugs and coverage metrics.

Job Details

In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Furthermore, you will learn to develop verification plans for all features under your care, execute verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage.

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