Design Verification Lead, Silicon

Minimum qualifications:

• Bachelor's degree in Computer Science or Electrical Engineering or equivalent practical experience.
• 5 years of experience in driving/leading functional verification for Intellectual Properties (IPs) and System-on-a-Chip (SoCs).
• Experience working with System Verilog and Universal Verification Methodology (UVM).

Preferred qualifications:

• Master's degree in Computer Science or Electrical Engineering or equivalent practical experience.
• Experience leading design verification of an SoC or large ASICs.
• Experience in scripting languages (e.g., Python, Perl) for automation and analysis.
• Technical experience in different verification techniques and methodologies, including formal, Gate Level Simulation, Unified Power Format based Power simulations, UVM, etc. to achieve bug-free Silicon in complex SoC.
• Experience in driving cross-functional teams for high quality tape-outs.