DFT Engineer

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

DFT Lead/Staff Engineer

Location: Austin, TX  

Responsibilities:
 

This position will be responsible for DFT Architecture including JTAG functionality, boundary scan, hierarchical scan, at- speed testing, I/ O testing requirements, MBIST and Repair, implement test logic for analog macros. The candidate should also be responsible to develop firmware driven cost-effective test strategies methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on ATE. This person should be capable of generate and debug DFT patterns on tester. 
 

Skills You Will Need 

Minimum qualifications:
 

• 5+ years in Industry
• Bachelor or Master’s degree in Electrical or Computer Engineering 
• Expert knowledge of DFT architecture on complex Design with multiple clock domains. 
• Experience in ATPG for pattern generation and simulation of Test Transition faults, Stuck-at, IDDQ, Bridging fault and Small delay defects . 
• Experience in industry standard DFT tools - Mentor Tessent suite, Synopsys DFT compiler. 
• Expert knowledge on scan coverage improvement and Test time reduction. 
• Experience with standard JTAG protocol and Boundary scan. 
• Should have participated in successful tapeouts of DSM SoC/ASIC chips at 40nm or below and achieved test targets. 
• Experience working with cross functional global teams 
• Experience in Low-Power DFT requirements. 
• Experience in Low-Power MBIST architectures and Memory testing. 

The following qualifications will be considered a plus: 

• Experience of working with Advantest, Teradyne testers. 
• Experience in DFT related RTL integration. 
• Excellent debugging and Scripting skills. 
• Excellent communication and analytical skills 
• Mentoring skills 
• Exceptional problem-solving skills

Benefits & Perks 

You can look forward to the following benefits:   
 

• Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental and vision plans
• Highly competitive salary
• 401k plan with match and Roth plan option
• Equity rewards (RSUs)
• Employee Stock Purchase Plan (ESPP)
• Life/AD&D and disability coverage
• Flexible spending accounts
• Adoption assistance
• Back-Up childcare
• Additional benefit options (Commuter benefits, Legal benefits, Pet insurance)
• Flexible PTO schedule
• 3 paid volunteer days per year
• Charitable contribution match
• Tuition reimbursement
• Free downtown parking
• Onsite gym
• Monthly wellness offerings
• Free snacks
• Monthly company updates with our CEO
   

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The annualized base pay range for this role is expected to be between $96,600 - $179,400 USD. Actual base pay could vary based on factors including but not limited to experience, geographic location where work will be performed and applicant’s skill set. The base pay is just one component of the total compensation package for employees. Other rewards may include an annual cash bonus, equity package and a comprehensive benefits package.

Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.