Digital Design Engineer, Principal
Job Description
- Bachelor’s degree in Computer Science, Electrical Engineering, or related field with 10–15 years of industry experience, or Master’s/PhD with 5–10 years.
- Deep, practical knowledge of System-on-Chip architecture, including processor cores, memory subsystems, and peripheral interfaces.
- Extensive experience creating and optimizing Verilog RTL, with expertise in Spyglass for LINT and Clock Domain Crossing (CDC) checks.
- Skilled in Perl and Python, using scripting to accelerate workflows and enhance efficiency.
- A track record of delivering production-quality designs on aggressive schedules.
- In-depth knowledge of IEEE 802.3 Ethernet standards.
- flexible time off
- 401k
- year-end shutdown
- floating holidays
- paid time off to volunteer
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
The Switch Business Unit in Marvell designs and develops the next generation AI datacenter System-On-Chip switch processors on leading edge process technology. We develop the architecture, collaborate on IP development, create the physical design, and work with the world’s leading AI data center and enterprise companies to bring next generation networking to reality.
What You Can Expect
As a Principal Design Engineer, you will be at the forefront of innovation—driving micro-architecture and RTL development while spearheading HW/SW co-design efforts that power the next generation of AI datacenter technologies. Collaborating with world-class, cross-functional teams, you’ll play a critical role in shaping cutting-edge System-on-Chip (SoC) solutions that set new standards for performance and efficiency.
Your Impact Will Include:
- Lead Micro-Architecture Vision: Architect and develop advanced SoC designs, including high-value IP blocks such as Ethernet MAC, PCS, and packet processing engines, to enable next-generation networking performance.
- Deliver Complex, High-Performance Solutions: Partner with architects and verification engineers to design, validate, and optimize sophisticated, timing-critical systems—mastering every stage of the SoC front-end design flow, from timing closure to power optimization.
What We're Looking For
- Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 10–15 years of hands-on industry experience, or a Master’s/PhD with 5–10 years of groundbreaking work in digital IC design.
- Deep, practical knowledge of System-on-Chip architecture, including processor cores, memory subsystems, and peripheral interfaces gained through real-world design challenges.
- Extensive experience creating and optimizing Verilog RTL, with expertise in Spyglass for thorough LINT and Clock Domain Crossing (CDC) checks to ensure flawless implementation.
- Skilled in Perl and Python, using scripting to accelerate workflows, enhance efficiency, and tackle complex design tasks.
- A track record of delivering production-quality designs on aggressive schedules, demonstrating exceptional problem-solving and innovation under pressure.
- In-depth knowledge of IEEE 802.3 Ethernet standards, ensuring cutting-edge performance and industry compliance in high-speed networking solutions.
Expected Base Pay Range (USD)
146,850 - 220,000, $ per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.
Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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