IC Design Engineer (DFT)

17 Minutes ago • All levels
Testing

Job Description

Broadcom is seeking an IC Design Engineer with expertise in Design for Testability (DFT) to join their team in Shanghai, China. The role involves participating in chip-level DFT architecture definition, implementing DFT schemes like scan, boundary scan, Mem BIST, and Logic BIST, and verifying DFT logics and test patterns through simulation. The engineer will also be responsible for test modes static timing analysis and supporting ATE bring-up and debugging DFT patterns. Candidates should possess a strong understanding of DFT methodologies and familiarity with industry-standard DFT tools.
Must Have:
  • Participate in chip level DFT architecture definition
  • Implement DFT schemes, including scan, boundary scan, Mem BIST and Logic BIST
  • Verify all DFT logics and test patterns with simulation
  • Test modes static timing analysis
  • Participate in ATE bring-up and debug the DFT patterns on ATE
  • Good understanding of the General DFT methodology such as BIST, SCAN, JTAG, ATPG and SSN
  • Familiarity with Mentor / Synopsys DFT flow and tools
  • Experience in developing constraints for synthesis/STA
  • Multi-mode, multi-corner STA experience in 16nm and lower technology nodes, Understanding Sign-Off Checks
  • Experience in silicon debug, diagnosis and yield improvement
  • MS Preferred Major: Microelectronics or related discipline

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Job Description:

Responsibilities:

  • Participate in chip level DFT architecture definition.
  • Implement DFT schemes, including scan, boundary scan, Mem BIST and Logic BIST.
  • Verify all DFT logics and test patterns with simulation
  • Test modes static timing analysis
  • Participate in ATE bring-up and debug the DFT patterns on ATE.

Requirements/Qualifications:

  • Good understanding of the General DFT methodology such as BIST, SCAN, JTAG, ATPG and SSN
  • Be familiar with Mentor / Synopsys DFT flow and tools
  • Experience in developing constraints for synthesis/STA
  • Multi-mode, multi-corner STA experience in 16nm and lower technology nodes, Understanding Sign-Off Checks
  • Experience in silicon debug, diagnosis and yield improvement

Education/Certifications

Preferred Degree: MS Preferred Major: Microelectronics or related discipline

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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