Integrity Sr. Manager

1 Month ago • 15 Years + • $163,800 PA - $262,000 PA

Job Summary

Job Description

The Integrity Sr. Manager will lead and manage overall SI and PI methodology with a talented team, designing and optimizing SERDES channels, creating PCB structure models, and establishing design trade-offs. The role involves working with various teams, evaluating PCB materials, owning VNA measurements, and leading system feasibility studies. The manager will also be responsible for generating specifications, guidelines, and system design rules. Additional responsibilities include managing projects, communicating technical concepts, defining requirements, providing SI models, and supporting customer analysis and debug efforts.
Must have:
  • Minimum 15 years of experience with 5 in management.
  • Experience in signal integrity and high speed system design.
  • Experience with post-layout extraction.
Good to have:
  • Strong foundation in digital signal processing.
  • Experience with Ethernet Standards.
Perks:
  • Medical, dental and vision plans
  • 401(K) participation including company matching
  • Employee Stock Purchase Program (ESPP)
  • Employee Assistance Program (EAP)
  • Company paid holidays, paid sick leave and vacation time

Job Details

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Job Description:

Broadcom's Core Switching Group (CSG) is looking for a highly skilled and hands-on Signal Integrity Sr. Manager to become a key member of the hardware development team. You will work with cross-functional teams to drive system architecture and design cutting-edge systems with flagship CSG switch devices, including the Tomahawk product family.

CSG develops large, highly integrated Ethernet Switches for diverse market segments, from Enterprise to MSDC. As part of a vertically integrated team, we design and build reference systems (224G PAM4 and beyond), while driving the ecosystem to support future-generation technologies. Come and join our innovative and fun team to help create industry-leading solutions for both Broadcom and our customers.

Responsibilities

  • Lead and manage overall SI and PI methodology with a very talented team.

  • Design, optimize, simulate, and validate SERDES channels (200Gbps and beyond), including  PCB segments (e.g. BGA escape, connector escape, etc).

  • Create and optimize complex PCB structure models with EM field solvers (Ansys HFSS, etc) and perform post-layout extractions. 

  • Establish design trade-offs between package, PCB and interconnects.

  • Work closely with SERDES IP, Packaging, PCB teams, and suppliers to drive solutions.

  • Evaluate PCB materials and connector solutions for next-gen designs.

  • Own VNA measurements for correlations and debug.

  • Lead next-generation system feasibility studies, assessing new approaches and solutions.

  • Influence industry methodology by addressing implementation constraints.

  • Drive methodology improvements and automation to optimize scalable SI workflows

  • Generate specifications, guidelines and system design rules for internal development and customers

Additional Responsibilities

  • Manage multiple projects simultaneously, ensuring timely delivery and quality.

  • Communicate complex technical concepts effectively in presentations, written documentation, and meetings.

  • Define and document requirements for packages and PCB designs, integrating industry standards, customer needs  and internal performance goals

  • Provide SI models with detailed documentation for both customer and internal engineers

  • Support customer analysis and debug efforts

Required Qualifications

  • Degree Electrical Engineering or Physics or related field.

  • Minimum of 15 years of overall experience of which a minimum of 5 years is in management.

  • Extensive hands-on experience in signal integrity, high speed/RF system design, and channel modeling

  • Proven track record in tuning and optimizing high layer count PCB structures

  • Experience with post-layout extraction

  • Deep understanding of PCB fabrication techniques and their limitations

  • Proficient with VNA, probing stations, spectrum analyzers, and scopes.

  • Experience with Cadence Allegro tools for layout reviews.

  • Strong hands-on debugging experience with SERDES channels

  • Familiarity with AMI SERDES models

  • Proficient in scripting and automation to optimize workflows.

  • Strong foundation in digital signal processing (Desired)

  • Experience with Ethernet Standards (Desired)

Tools

  • EM modeling: Ansys HFSS, SIWave, Q3D, Simbeor

  • Circuit simulation: Keysight ADS

  • Programming/Scripting: Matlab (desired), Python, etc

Layout Tools: Cadence APD/Allegro (desired)

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $163,800  - $262,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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