Memory System Designer and Place and Route Engineer

9 Minutes ago • 8 Years + • $108,000 PA - $172,800 PA
System Design

Job Description

Broadcom is seeking an energetic and passionate design engineer for its Central Engineering Group. The role involves joining a memory subsystem design team responsible for developing large memory blocks and subsystems. Key responsibilities include architecting and designing memory subsystems, implementing RTL, performing place and route (physical design), and ensuring design closure for timing, DRC, LVS, and EM/IR, as well as gate netlist synthesis. A minimum of 8 years of relevant experience and a Bachelor's in Electrical Engineering are typically required.
Must Have:
  • Architect and design memory subsystems
  • Implement RTL designs
  • Perform place and route (physical design)
  • Ensure design closure (timing, DRC, LVS, EM/IR)
  • Perform gate netlist synthesis
  • Strong design skills
  • Verilog RTL coding and debugging
  • Expertise in place and route
  • Proficiency with STA, DRC, EM/IR tools
  • Python coding ability
  • Understanding of synthesis tools
  • Logical equivalency checking
  • Familiarity with memory behavior
  • Automation scripting proficiency
Perks:
  • Medical, dental and vision plans
  • 401(K) participation including company matching
  • Employee Stock Purchase Program (ESPP)
  • Employee Assistance Program (EAP)
  • Company paid holidays
  • Paid sick leave
  • Vacation time
  • Paid Family Leave and other leaves of absence

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We are looking for an energetic and passionate design engineer to join our Central Engineering Group and be part of a memory subsystem design team responsible for the development of large memory blocks and subsystems. Typically requires a minimum of 8 years of relevant experience and a Bachelor in Electrical Engineering.

Job Responsibilities

  • Architect and design memory subsystems
  • Implement RTL of subsystem designs
  • Place and route (physical design)
  • Design closure: timing, DRC, LVS, EM/IR, etc.
  • Gate netlist synthesis

Skill Set Required

  • Strong design skills
  • Ability to write and debug Verilog RTL code
  • Place and route expertise
  • Proficient in running STA, DRC, EM/IR tools, and attaining design closure
  • Ability to code in Python
  • Good understanding of synthesis tools and running synthesis
  • Capable of running and debugging logical equivalency checkers
  • Familiar with memory behavior
  • Proficient in writing automation scripts, and tools savvy
  • Good communication, interpersonal, and leadership skills
  • Motivated, self-driven, and good at multitasking

Compensation and Benefits

The annual base salary range for this position is $108,000 - $172,800

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Welcome! Thank you for your interest in !

We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

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