MTS IC-Advance Packaging Design Engineer

1 Year ago • All levels

Job Summary

Job Description

Experienced IC Advance Package Design Engineer with strong APR coding, Interposer design, and CAD Layout skills. Must have experience with Cadence SIP, APD or XPD.
Must have:
  • APR coding
  • Interposer design
  • Cadence SIP
  • XPD Layout
Good to have:
  • Signal Integrity
  • Power Integrity
  • Perl Python
  • EDA tool coding
Perks:
  • AMD Benefits
  • Inclusive Culture

Job Details

Overview:
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
Responsibilities:
MTS IC-Advance Packaging Design Engineer

THE ROLE:
The candidate is an experienced IC Advance Package Design MTS Engineer that has excellent communication & project management skills and can complete the design task with least supervision. He/she must be able to work on a fast phase environment and collaborate well with others.

THE PERSON:
The successful candidates must be a team player with a commitment to meeting deadlines, have a drive for solutions and an aptitude to thrive with the ability to work in a fast-paced multi-tasking environment. He or she would have excellent cross functional project management skills, conflict management skills, strong interpersonal skills with good executive presentation & communication skills. Demonstrating strong leadership to excel in his/her work with minimum supervision and strong interest to grow in people management ladder.

KEY RESPONSIBILITIES:
  • Contribute to the developments and enhancements of design methodologies to improve design cycle time.
  • Support evaluation of new design flow and prepare testcases for APR flow.
  • Support Package design team to define tool roadmap that will meet the design objectives for performance, cost, and quality for advance package design.
  • Support substrate design, advance package design and test vehicles for product design roadmap and feasibility.
  • Support package team to complete Bump design and respective flow definition

PREFERRED EXPERIENCE:
  • Strong Experience in APR coding specific to ICC2 or 3DIC Compiler
  • Experience in Interposer design for 2.5D, COWOS, INFO and other 3D advanced packaging technologies (Chiplet)
  • Well experienced in using CAD Layout tools such as Cadence SIP, APD or XPD, and other Silicon Physical Layout tool
  • Very good understanding of Signal Integrity and power integrity principles
  • Very good Knowledge on Perl and Python Programming
  • Experience in EDA tool algorithm and coding development is a definite plus
  • Experience in dealing with assembly, foundry, and substrate vendors is a plus

ACADEMIC CREDENTIALS:
  • Masters in electrical engineering, Computer Engineering, or Engineering Science

LOCATION:
India/Bangalore

#LI-RP1
Qualifications:
Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

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