PMTS Silicon Design Engineer

THE ROLE (SOC DV - Technical Lead):

• Drive and lead SOC DV activities after having co-ordination with various IPs, SOC (Design, DFT, PD), System and SW engineering teams.
• Expertise in multiple SOC functional domains with deeper SOC architecture understanding of X86/ARM core based SOC’s
• Able to take complete functional verification ownership of one or more SOC’s.
• Work with customer on feature requirements, use case scenarios, test plan reviews to realize the SOC is meeting all functional aspects of the targeted domain.
• Work with architecture and design team on high level arch, Integration, use case scenarios, config space etc. Work with IP team for IP Integration, IP requirement and deliverables.
• Work with vendors and ODC/CW members for the successful project execution.
• Work with program management team and SOC management for SOC planning, schedule, critical path analysis, risk mitigation and Quality deliverable. Work with post-Si team to drive Si bring up and ramp to productization.

THE PERSON:

• Leader with strong self-driving ability
• Need excellent communication skills (both written and oral)
• Strong problem-solving skills, go to person for SOC DV activities.

KEY RESPONSIBILITIES:

• Responsible for the quality of the deliverables from SOC DV.
• Driving SOC DV including the IP integration and verification for different functions like Low power verification, Graphics and core data path, COH, Display, Memory Controllers, Emulation etc. from feature extraction to tape-out and productization support.
• Adapt the Design changes, Testbench Architect, Test-plan creation, Power Reduction, Timing Convergence, test bench and test plan reviews & tape-outs.
• Identify the key tools, evaluate the same and integrate if found to be useful for the team.
• Drive the connectivity as part of integration, have the associated assertions to have the SOC integration checks and drive for the automation to have all required methodologies in place.
• Running regular execution meetings, scrums, standing meetings and resolving bottlenecks.
• Drive the team for the bug free silicon deliverable and increase the efficiency by adapting the possible automation in the test bench, test cases and DV flows.

PREFERRED EXPERIENCE:

• Hands on experience in SOC DV using SV/uVM and C based test benches, considering as a senior IC role.
• Experience of successfully leading minimum 2 SOC execution in parallel from spec to tape-out.
• Expertise in IP, Subsystem and SOC Verification -with specialization in Integration, verification tools & methodology and SOC signoff.
• Work with a team of Architects, Hardware and Software engineers to Define the product use case scenarios.
• Strong hands-on experience in different SOC Verification activities, System Verilog, uVM, C++, HW/SW co-verification, Test plan review, Debug/triage, Coverage, bottleneck resolution, Strong Problem Solving skills, Automation and Debugging Skills, System bus protocol understanding (e.g. AXI, PCIe, DDR, memory etc.)
• Scripting such as Ruby, Perl, Shell, Python and TCL is a plus
• Comfortable with design/verification tools and flows like VCS, Verdi, SOC Connectivity, SV assertions, HW-SW co-simulations, UPF/CPF flows etc.
• Strong understanding of System integration, Make file flow, Verification Methodologies, Boot up sequence.
• Expertise in problem solving, Quality deliverables, Risk identification and mitigation, critical path analysis.
• JIRA based project management is a plus.

ACADEMIC CREDENTIALS:

• BE/B.Tech/ME/MTECH/MS or equivalent in ECE/EEE/CSE
• ~17-22 years of strong experience in SoC DV, IP and Sub System DV, Technical leadership of SOC DV.

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