Principal Engineer - STA

What you'll need:

• Good understanding of overall design Flow RTL to GDS.

• Must have 14+ years of experience on signing off the full chip synthesis/STA for tape outs

• Hands on Experience on Both Block level and Full chip timing Constraints Development and Management for hierarchical designs.

• Deep Understanding of DFT Constraints.

• Hand on Synthesis & STA Experience on Lower node Technologies with Synopsys/Cadence Tools.

• good understanding of overall ASIC Physical Design/DFT, Tools and implication on Timing Convergence

• Must have in-depth understanding of relevant areas of Library / Memory / Other collaterals and dependencies on STA

• Must understand Ultra Submicron issues, Variation aware/Aging Aware Design Sign-off Must understand CTS/Other clock Distribution methodologies well.

• Good knowledge on Timing Budgets.

• Knowledge on Perl / TCL / Python scripting language

• Experience on multi voltage designs using CPF/UPF.

• Good understanding on timing/area/power/complexity tradeoffs on complex interface design

• Hands on experience on power analysis using PTPX

• Good understanding of VHDL / Verilog Constructs.

• Familiarity with IP level verification and strong RTL debugging capabilities is an added bonus

• A, enthusiastic team player who enjoys working with others

• Experience troubleshooting issues with users Experience communicating updates and resolutions to customers and other partners complex technical concepts to other design peers in verbal and written form

What You'll Do:

We are looking for experienced STA engineer to lead the timing convergence of the SoCs.Responsibilities include

• STA setup, convergence, reviews and sign-off for Multi-Mode and Multi-corner Multi voltage domain designs.

• Constraint Generation & Maintenance for Block / SOC for complex hierarchical Designs for all the Modes

• Timing analysis, and timing closure at Full chip level while supporting the PD team on Block/SS level timing convergence.

• Interaction with Design, DFT, IP&PD teams for Timing Convergence & Resolving Constraint Conflicts.

• Support Verification team to enable GLS.

• Guide the CTS strategies and provide feedback to Implementation Team.

• Manage the timing ECO generation and strategize the implementation methodology.

• Develop Automation scripts with-in STA tools for Methodology development.

• You will be reporting to Director - ASIC engineering.

'' We have a flexible work environment to support and help employees thrive in personal and professional capacities"

As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:

• Competitive Compensation Package

• Restricted Stock Units (RSUs)

• Provisions to pursue advanced education from Premium Institute, eLearning content providers

• Medical Insurance and a cohort of Wellness Benefits

• Educational Assistance

• Advance Loan Assistance

• Office lunch & Snacks Facility

Equal Employment Opportunity Statement

Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.