R&D Engineer - Analog Mask Layout

Broadcom Inc’s Mixed Signal ASICs Product Group (MSAP) is seeking a Senior/Staff Analog IC Layout Engineer to develop complex Analog/Mixed Signal circuit layouts in advanced deep sub-micron CMOS technologies. The role involves layout implementation of analog circuit schematics, verification to comply with IP specifications, and ensuring high manufacturing product yield. The candidate will discuss, floorplan, and design layouts using CADENCE Virtuoso, apply DFM best practices, and use Mentor Graphics CALIBRE for verification. This position requires understanding analog layout fundamentals, experience with device matching, EM, IR, and low noise requirements, and handling issues like Latch-up and ESD.

Must Have

• Implement analog layouts with device matching, EM, IR and low noise requirements
• Use CADENCE Virtuoso layout tools
• Interpret and debug using CALIBRE and other in-house tools
• Discuss, floorplan and design analog layout from analog/mixed signal circuit
• Understand analog layout fundamentals and DFM best practices
• Use Mentor Graphics CALIBRE verification tools (DRC/LVS/ERC/ANT)
• Knowledgeable in handling analog layout related issues such as Latch-up and ESD
• Prepare and conduct project layout reviews
• Work closely with fellow layout and design engineers

Good to Have

• Highly motivated team player
• Able to work independently
• Strong troubleshooting skills
• Strong communication skills
• Good interpersonal skills
• Creative skills
• Ability to multitask in a demanding and fast-paced environment

Job Description:

Roles:

Broadcom Inc’s Mixed Signal ASICs Product Group (MSAP) is looking for an IC professional to join our team as a Senior/Staff Analog IC Layout Engineer for the development of complex Analog/Mixed Signal circuit layouts in advanced deep sub-micron CMOS technologies for integration in Broadcom system-on-chip products. The role focuses on layout implementation of analog circuit schematics and verification to comply with IP specifications/requirements to ensure high manufacturing product yield.

The candidate should understand analog layout fundamentals and experienced in implementing analog layouts with device matching, EM, IR and low noise requirements. Hands on experience using CADENCE virtuoso layout tools is required. High level proficiency in interpretation and debug skills using CALIBRE and other in-house tools.

Highly motivated team player, able to work independently and demonstrate strong troubleshooting and communication skill. Good interpersonal and creative skills with the ability to multitask in a demanding and fast paced environment.

Responsibilities:

• Discuss, floorplan and design of analog layout from analog/mixed signal circuit using CADENCE virtuoso layout tool.
• Understand analog layout fundamentals and using DFM best practices to design quality layouts that comply with circuit requirements.
• Use Mentor Graphics CALIBRE verification tools (DRC/LVS/ERC/ANT) and other in-house DFM tools to check for design rule compliance.
• Knowledgeable in handling analog layout related issues such as Latch-up and ESD.
• Prepare and conduct project layout reviews with the team, take action on feedback received.
• Work closely with fellow layout engineers and design engineers at both local and remote locations.

Requirements:

• Minimum 5 years of experience in analog/mixed-signal layout design of deep sub-micron CMOS circuits (40nm/28nm/16nm).
• Bachelor’s degree in Electronics and Electrical Engineering or equivalent
• Experienced in using CADENCE Virtuoso XL layout tools and CALIBRE verification tools.